68                            const DebugLoc &DL, unsigned Reg, unsigned Lane,
74                                  unsigned Lane, const TargetRegisterClass *TRC);
88                                 unsigned Lane, unsigned ToInsert);
416                                        unsigned Lane, bool QPR) {  in createDupLane()  argument
422       .addImm(Lane)  in createDupLane()
431     const DebugLoc &DL, unsigned DReg, unsigned Lane,  in createExtractSubreg()  argument
438     .addReg(DReg, 0, Lane);  in createExtractSubreg()
476     const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {  in createInsertSubreg()  argument
484     .addImm(Lane);  in createInsertSubreg()
541     unsigned Lane;  in optimizeAllLanesPattern()  local
543       case ARM::ssub_0: Lane = 0; break;  in optimizeAllLanesPattern()
544       case ARM::ssub_1: Lane = 1; break;  in optimizeAllLanesPattern()
554     Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);  in optimizeAllLanesPattern()