| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankLegalizeHelper.h | 39 static constexpr LLT S1 = LLT::scalar(1);
40 static constexpr LLT S16 = LLT::scalar(16);
41 static constexpr LLT S32 = LLT::scalar(32);
42 static constexpr LLT S64 = LLT::scalar(64);
43 static constexpr LLT S96 = LLT::scalar(96);
44 static constexpr LLT S128 = LLT::scalar(128);
45 static constexpr LLT S256 = LLT::scalar(256);
47 static constexpr LLT V2S16 = LLT::fixed_vector(2, 16);
48 static constexpr LLT V4S16 = LLT::fixed_vector(4, 16);
49 static constexpr LLT V6S16 = LLT::fixed_vector(6, 16);
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| H A D | AMDGPULegalizerInfo.cpp | 56 static LLT getPow2VectorType(LLT Ty) { in getPow2VectorType()
63 static LLT getPow2ScalarType(LLT Ty) { in getPow2ScalarType()
66 return LLT::scalar(Pow2Bits); in getPow2ScalarType()
74 const LLT Ty = Query.Types[TypeIdx]; in isSmallOddVector()
78 const LLT EltTy = Ty.getElementType(); in isSmallOddVector()
88 const LLT Ty = Query.Types[TypeIdx]; in sizeIsMultipleOf32()
95 const LLT Ty = Query.Types[TypeIdx]; in isWideVec16()
96 const LLT EltTy = Ty.getScalarType(); in isWideVec16()
103 const LLT Ty = Query.Types[TypeIdx]; in oneMoreElement()
104 const LLT EltTy = Ty.getElementType(); in oneMoreElement()
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| H A D | AMDGPURegBankLegalizeHelper.cpp | 60 ArrayRef<LLT> LLTBreakdown, LLT MergeTy) { in splitLoad()
67 LLT PtrTy = MRI.getType(Base); in splitLoad()
69 LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); in splitLoad()
73 for (LLT PartTy : LLTBreakdown) { in splitLoad()
108 void RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy, in widenLoad()
109 LLT MergeTy) { in widenLoad()
126 LLT DstTy = MRI.getType(Dst); in widenLoad()
138 LLT Ty = MRI.getType(Dst); in lowerVccExtToSel()
235 assert(MRI.getType(Dst) == LLT::scalar(64)); in lowerV_BFE()
294 LLT Ty = MRI.getType(DstReg); in lowerS_BFE()
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| H A D | AMDGPUArgumentUsageInfo.cpp | 89 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
95 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32)); in getPreloadedValue()
100 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); in getPreloadedValue()
103 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
106 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
109 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
112 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
116 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
119 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)}; in getPreloadedValue()
123 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); in getPreloadedValue()
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| H A D | AMDGPURegBankLegalizeRules.cpp | 29 bool AMDGPU::isAnyPtr(LLT Ty, unsigned Width) { in isAnyPtr()
50 return MRI.getType(Reg) == LLT::scalar(1); in matchUniformityAndLLT()
52 return MRI.getType(Reg) == LLT::scalar(16); in matchUniformityAndLLT()
54 return MRI.getType(Reg) == LLT::scalar(32); in matchUniformityAndLLT()
56 return MRI.getType(Reg) == LLT::scalar(64); in matchUniformityAndLLT()
58 return MRI.getType(Reg) == LLT::scalar(128); in matchUniformityAndLLT()
60 return MRI.getType(Reg) == LLT::pointer(0, 64); in matchUniformityAndLLT()
62 return MRI.getType(Reg) == LLT::pointer(1, 64); in matchUniformityAndLLT()
64 return MRI.getType(Reg) == LLT::pointer(3, 32); in matchUniformityAndLLT()
66 return MRI.getType(Reg) == LLT::pointer(4, 64); in matchUniformityAndLLT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVLegalizerInfo.cpp | 29 const LLT Ty = Query.Types[TypeIdx]; in typeOfExtendedScalars()
40 const LLT s1 = LLT::scalar(1); in SPIRVLegalizerInfo()
41 const LLT s8 = LLT::scalar(8); in SPIRVLegalizerInfo()
42 const LLT s16 = LLT::scalar(16); in SPIRVLegalizerInfo()
43 const LLT s32 = LLT::scalar(32); in SPIRVLegalizerInfo()
44 const LLT s64 = LLT::scalar(64); in SPIRVLegalizerInfo()
46 const LLT v16s64 = LLT::fixed_vector(16, 64); in SPIRVLegalizerInfo()
47 const LLT v16s32 = LLT::fixed_vector(16, 32); in SPIRVLegalizerInfo()
48 const LLT v16s16 = LLT::fixed_vector(16, 16); in SPIRVLegalizerInfo()
49 const LLT v16s8 = LLT::fixed_vector(16, 8); in SPIRVLegalizerInfo()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/ |
| H A D | LowLevelType.h | 40 class LLT {
43 static constexpr LLT scalar(unsigned SizeInBits) { in scalar()
44 return LLT{/*isPointer=*/false, /*isVector=*/false, /*isScalar=*/true, in scalar()
50 static constexpr LLT token() { in token()
51 return LLT{/*isPointer=*/false, /*isVector=*/false, in token()
58 static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits) { in pointer()
60 return LLT{/*isPointer=*/true, /*isVector=*/false, /*isScalar=*/false, in pointer()
65 static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits) { in vector()
67 return LLT{/*isPointer=*/false, /*isVector=*/true, /*isScalar=*/false, in vector()
72 static constexpr LLT vector(ElementCount EC, LLT ScalarTy) { in vector()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.h | 106 LLT NarrowTy);
112 LLT WideTy);
115 LLVM_ABI LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
119 LLVM_ABI LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
124 unsigned TypeIdx, LLT NarrowTy);
129 LLT MoreTy);
142 LLVM_ABI void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
148 LLVM_ABI void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
153 LLVM_ABI void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
159 LLVM_ABI void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
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| H A D | LegalizerInfo.h | 113 ArrayRef<LLT> Types;
116 LLT MemoryTy;
121 MemDesc(LLT MemoryTy, uint64_t AlignInBits, AtomicOrdering Ordering) in MemDesc()
132 constexpr LegalityQuery(unsigned Opcode, ArrayRef<LLT> Types,
148 LLT NewType;
151 const LLT NewType) in LegalizeActionStep()
201 std::function<std::pair<unsigned, LLT>(const LegalityQuery &)>;
205 LLT Type0;
206 LLT Type1;
207 LLT MemTy;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCLegalizerInfo.cpp | 23 const LLT QueryTy = Query.Types[TypeIdx]; in isRegisterType()
41 const LLT P0 = LLT::pointer(0, 64); in PPCLegalizerInfo()
42 const LLT S1 = LLT::scalar(1); in PPCLegalizerInfo()
43 const LLT S8 = LLT::scalar(8); in PPCLegalizerInfo()
44 const LLT S16 = LLT::scalar(16); in PPCLegalizerInfo()
45 const LLT S32 = LLT::scalar(32); in PPCLegalizerInfo()
46 const LLT S64 = LLT::scalar(64); in PPCLegalizerInfo()
47 const LLT V16S8 = LLT::fixed_vector(16, 8); in PPCLegalizerInfo()
48 const LLT V8S16 = LLT::fixed_vector(8, 16); in PPCLegalizerInfo()
49 const LLT V4S32 = LLT::fixed_vector(4, 32); in PPCLegalizerInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalityPredicates.cpp | 28 LegalityPredicate LegalityPredicates::typeIs(unsigned TypeIdx, LLT Type) { in typeIs()
35 std::initializer_list<LLT> TypesInit) { in typeInSet()
36 SmallVector<LLT, 4> Types = TypesInit; in typeInSet()
44 std::initializer_list<std::pair<LLT, LLT>> TypesInit) { in typePairInSet() argument
45 SmallVector<std::pair<LLT, LLT>, 4> Types = TypesInit; in typePairInSet()
47 std::pair<LLT, LLT> Match = {Query.Types[TypeIdx0], Query.Types[TypeIdx1]}; in typePairInSet()
54 std::initializer_list<std::tuple<LLT, LLT, LLT>> TypesInit) { in typeTupleInSet() argument
55 SmallVector<std::tuple<LLT, LLT, LLT>, 4> Types = TypesInit; in typeTupleInSet()
57 std::tuple<LLT, LLT, LLT> Match = { in typeTupleInSet()
99 LLT Ty = Query.Types[TypeIdx]; in isPointer()
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| H A D | LegalizeMutations.cpp | 17 LegalizeMutation LegalizeMutations::changeTo(unsigned TypeIdx, LLT Ty) { in changeTo()
32 const LLT OldTy = Query.Types[TypeIdx]; in changeElementTo()
33 const LLT NewTy = Query.Types[FromTypeIdx]; in changeElementTo()
39 LLT NewEltTy) { in changeElementTo()
41 const LLT OldTy = Query.Types[TypeIdx]; in changeElementTo()
49 const LLT OldTy = Query.Types[TypeIdx]; in changeElementCountTo()
50 const LLT NewTy = Query.Types[FromTypeIdx]; in changeElementCountTo()
58 LLT NewEltTy) { in changeElementCountTo()
60 const LLT OldTy = Query.Types[TypeIdx]; in changeElementCountTo()
70 const LLT OldTy = Query.Types[TypeIdx]; in changeElementSizeTo()
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| H A D | LegalizerHelper.cpp | 57 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { in getNarrowTypeBreakDown()
74 LLT::scalarOrVector(ElementCount::getFixed(LeftoverSize / EltSize), in getNarrowTypeBreakDown()
77 LeftoverTy = LLT::scalar(LeftoverSize); in getNarrowTypeBreakDown()
84 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { in getFloatTypeForLLT()
164 LLT ResultTy, LLT PartTy, in insertParts()
166 LLT LeftoverTy, in insertParts()
192 LLT GCDTy = getGCDType(getGCDType(ResultTy, LeftoverTy), PartTy); in insertParts()
195 LLT ResultLCMTy = buildLCMMergePieces(ResultTy, LeftoverTy, GCDTy, GCDRegs); in insertParts()
201 LLT Ty = MRI.getType(Reg); in appendVectorElts()
237 LLT GCDTy, Register SrcReg) { in extractGCDType()
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| H A D | CallLowering.cpp | 161 LLT Ty = getLLTForType(*F->getType(), DL); in lowerCall()
329 LLT LLTy = MRI.getType(DstRegs[0]); in mergeVectorRegsToResultRegs()
330 LLT PartLLT = MRI.getType(SrcRegs[0]); in mergeVectorRegsToResultRegs()
333 LLT LCMTy = getCoverTy(LLTy, PartLLT); in mergeVectorRegsToResultRegs()
373 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, in buildCopyFromRegs()
399 LLT LocTy = MRI.getType(SrcReg); in buildCopyFromRegs()
410 LLT OrigTy = MRI.getType(OrigRegs[0]); in buildCopyFromRegs()
412 LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits()); in buildCopyFromRegs()
423 LLT OrigTy = MRI.getType(OrigRegs[0]); in buildCopyFromRegs()
429 auto Widened = B.buildMergeLikeInstr(LLT::scalar(SrcSize), Regs); in buildCopyFromRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGenTypes/ |
| H A D | LowLevelType.cpp | 19 LLT::LLT(MVT VT) { in LLT() function in LLT
38 void LLT::print(raw_ostream &OS) const { in print()
52 LLVM_DUMP_METHOD void LLT::dump() const { in dump()
58 const constexpr LLT::BitFieldInfo LLT::ScalarSizeFieldInfo;
59 const constexpr LLT::BitFieldInfo LLT::PointerSizeFieldInfo;
60 const constexpr LLT::BitFieldInfo LLT::PointerAddressSpaceFieldInfo;
61 const constexpr LLT::BitFieldInfo LLT::VectorElementsFieldInfo;
62 const constexpr LLT::BitFieldInfo LLT::VectorScalableFieldInfo;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86LegalizerInfo.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 37 std::initializer_list<LLT> IntOrFPVecTys, in typeIsLegalIntOrFPVec()
51 typeIsLegalBoolVec(unsigned TypeIdx, std::initializer_list<LLT> BoolVecTys, in typeIsLegalBoolVec()
62 std::initializer_list<LLT> PtrVecTys, in typeIsLegalPtrVec()
75 : STI(ST), XLen(STI.getXLen()), sXLen(LLT::scalar(XLen)) { in RISCVLegalizerInfo()
76 const LLT sDoubleXLen = LLT::scalar(2 * XLen); in RISCVLegalizerInfo()
77 const LLT p0 = LLT::pointer(0, XLen); in RISCVLegalizerInfo()
78 const LLT s1 = LLT::scalar(1); in RISCVLegalizerInfo()
79 const LLT s8 = LLT::scalar(8); in RISCVLegalizerInfo()
80 const LLT s16 = LLT::scalar(16); in RISCVLegalizerInfo()
81 const LLT s32 = LLT::scalar(32); in RISCVLegalizerInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86LegalizerInfo.cpp | 51 const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0)); in X86LegalizerInfo()
52 const LLT s1 = LLT::scalar(1); in X86LegalizerInfo()
53 const LLT s8 = LLT::scalar(8); in X86LegalizerInfo()
54 const LLT s16 = LLT::scalar(16); in X86LegalizerInfo()
55 const LLT s32 = LLT::scalar(32); in X86LegalizerInfo()
56 const LLT s64 = LLT::scalar(64); in X86LegalizerInfo()
57 const LLT s80 = LLT::scalar(80); in X86LegalizerInfo()
58 const LLT s128 = LLT::scalar(128); in X86LegalizerInfo()
59 const LLT sMaxScalar = Subtarget.is64Bit() ? s64 : s32; in X86LegalizerInfo()
60 const LLT v2s32 = LLT::fixed_vector(2, 32); in X86LegalizerInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LowLevelTypeUtils.cpp | 20 LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) { in getLLTForType()
23 LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL); in getLLTForType()
26 return LLT::vector(EC, ScalarTy); in getLLTForType()
31 return LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); in getLLTForType()
39 return LLT::scalar(SizeInBits); in getLLTForType()
43 return LLT::token(); in getLLTForType()
45 return LLT(); in getLLTForType()
48 MVT llvm::getMVTForLLT(LLT Ty) { in getMVTForLLT()
57 EVT llvm::getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx) { in getApproximateEVTForLLT()
66 LLT llvm::getLLTForMVT(MVT Ty) { in getLLTForMVT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 44 const LLT p0 = LLT::pointer(0, 64); in AArch64LegalizerInfo()
45 const LLT s8 = LLT::scalar(8); in AArch64LegalizerInfo()
46 const LLT s16 = LLT::scalar(16); in AArch64LegalizerInfo()
47 const LLT s32 = LLT::scalar(32); in AArch64LegalizerInfo()
48 const LLT s64 = LLT::scalar(64); in AArch64LegalizerInfo()
49 const LLT s128 = LLT::scalar(128); in AArch64LegalizerInfo()
50 const LLT v16s8 = LLT::fixed_vector(16, 8); in AArch64LegalizerInfo()
51 const LLT v8s8 = LLT::fixed_vector(8, 8); in AArch64LegalizerInfo()
52 const LLT v4s8 = LLT::fixed_vector(4, 8); in AArch64LegalizerInfo()
53 const LLT v2s8 = LLT::fixed_vector(2, 8); in AArch64LegalizerInfo()
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| H A D | AArch64PreLegalizerCombiner.cpp | 84 LLT LHSTy = MRI.getType(LHS); in matchICmpRedundantTrunc()
95 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
109 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
228 B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset))); in applyFoldGlobalOffset()
244 LLT DstTy = MRI.getType(DstReg); in matchExtAddvToUdotAddv()
245 LLT MidTy = MRI.getType(MidReg); in matchExtAddvToUdotAddv()
249 LLT SrcTy; in matchExtAddvToUdotAddv()
261 LLT Ext1DstTy = MRI.getType(ExtMI1->getOperand(0).getReg()); in matchExtAddvToUdotAddv()
262 LLT Ext2DstTy = MRI.getType(ExtMI2->getOperand(0).getReg()); in matchExtAddvToUdotAddv()
316 LLT SrcTy = MRI.getType(Ext1SrcReg); in applyExtAddvToUdotAddv()
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| H A D | AArch64InstructionSelector.cpp | 194 bool tryOptConstantBuildVec(MachineInstr &MI, LLT DstTy,
321 const RegisterBank &DstRB, LLT ScalarTy,
571 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank()
778 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
995 LLT Ty = MRI.getType(Reg); in selectDebugInstr()
1105 static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) { in selectFPConvOpc()
1189 LLT Ty = MRI.getType(True); in emitSelect()
1605 LLT Ty = MRI.getType(TestReg); in emitTestBit()
1846 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
1866 static std::optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, in getVectorSHLImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kLegalizerInfo.cpp | 24 const LLT s8 = LLT::scalar(8); in M68kLegalizerInfo()
25 const LLT s16 = LLT::scalar(16); in M68kLegalizerInfo()
26 const LLT s32 = LLT::scalar(32); in M68kLegalizerInfo()
27 const LLT p0 = LLT::pointer(0, 32); in M68kLegalizerInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 197 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
232 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
242 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
255 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
262 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
276 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
277 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
285 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
286 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
295 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 23 LLT ValTy;
24 LLT PtrTy;
64 std::initializer_list<LLT> SupportedValues) { in CheckTyN()
71 const LLT s1 = LLT::scalar(1); in MipsLegalizerInfo()
72 const LLT s8 = LLT::scalar(8); in MipsLegalizerInfo()
73 const LLT s16 = LLT::scalar(16); in MipsLegalizerInfo()
74 const LLT s32 = LLT::scalar(32); in MipsLegalizerInfo()
75 const LLT s64 = LLT::scalar(64); in MipsLegalizerInfo()
76 const LLT v16s8 = LLT::fixed_vector(16, 8); in MipsLegalizerInfo()
77 const LLT v8s16 = LLT::fixed_vector(8, 16); in MipsLegalizerInfo()
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