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Searched refs:LDR (Results 1 – 25 of 37) sorted by relevance

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/freebsd/stand/i386/pxeldr/
H A DMakefile3 PROG= ${LDR}
7 SRCS= ${LDR}.S
11 LDR= pxeldr macro
40 ${BOOT}: ${LDR} ${LOADER}
41 cat ${LDR} ${LOADER} > ${.TARGET}.tmp
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_trampoline_arm.S26 LDR r2, [pc, r1]
58 LDR r2, [pc, r1]
89 LDR r2, [pc, r1]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredNeoverse.td21 // Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions
H A DAArch64SchedExynosM3.td522 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
524 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
566 def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
569 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
570 def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
572 ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
574 ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
H A DAArch64SchedTSV110.td440 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(W|X)l$")>;
443 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)ui$")>;
446 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
525 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[DSQ]l")>;
527 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ](post|pre)")>;
528 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ]ui")>;
529 def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
H A DAArch64SchedExynosM4.td617 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
619 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
679 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
682 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
683 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
685 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
687 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
H A DAArch64SchedExynosM5.td674 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
676 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
735 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
738 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
739 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
741 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
743 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
H A DAArch64SchedFalkorDetails.td1092 (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>;
1094 (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>;
1098 (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
1174 (instregex "^LDR(BB|HH|W|X)ui$")>;
1176 (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
1178 (instregex "^LDR(BB|HH|W|X)ro(W|X)$")>;
1180 (instregex "^LDR(W|X)l$")>;
H A DAArch64SchedNeoverseN1.td475 def : InstRW<[N1Write_5c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$",
481 (instregex "^LDR[BHSDQ](post|pre)$")>;
484 def : InstRW<[N1Write_5c_1I_1L], (instregex "^LDR[BHSDQ]ui$")>;
490 def : InstRW<[N1Write_5c_1I_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;
494 def : InstRW<[N1Write_6c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;
H A DAArch64SchedAmpere1.td801 def : InstRW<[Ampere1Write_6cyc_1AB_1L], (instregex "LDR[BHSDQ]ro(W|X)")>;
964 (instregex "LDR(B|D|H|Q|S)ui")>;
966 (instregex "LDR(D|Q|W|X)l")>;
976 (instregex "LDR(HH|SHW|SHX|W|X)ro(W|X)")>;
H A DAArch64SchedAmpere1B.td767 def : InstRW<[Ampere1BWrite_4cyc_1L], (instregex "LDR[BHSDQ]ro(W|X)")>;
946 (instregex "LDR(B|D|H|Q|S)ui")>;
948 (instregex "LDR(D|Q|W|X)l")>;
958 (instregex "LDR(HH|SHW|SHX|W|X)ro(W|X)")>;
H A DAArch64SchedKryoDetails.td1462 (instregex "LDR((D|S)l|(D|S|H|B)ui)")>;
1474 (instregex "LDR(D|S|H|B)ro(W|X)")>;
1480 (instregex "LDR(D|S|H|B)(post|pre)")>;
1486 (instregex "LDR(BB|HH|W|X)ui")>;
1492 (instregex "LDR(BB|HH|W|X)(post|pre)")>;
1498 (instregex "(LDR(BB|HH|W|X)ro(W|X)|PRFMro(W|X))")>;
H A DAArch64SchedNeoverseN2.td857 def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[SDQ]l$",
861 def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
863 def : InstRW<[WriteAdr, N2Write_6cyc_1I_1L], (instregex "^LDR[BHSDQ]pre$")>;
866 def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
872 def : InstRW<[N2Write_6cyc_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;
876 def : InstRW<[N2Write_7cyc_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;
H A DAArch64SchedNeoverseV1.td733 def : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$",
735 "^LDR[BHSDQ]ui$")>;
740 (instregex "^LDR[BHSDQ](post|pre)$")>;
746 def : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;
750 def : InstRW<[V1Write_7c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;
H A DAArch64SchedCyclone.td243 // EXAMPLE: LDR Xn, Xm [, lsl 3]
256 // EXAMPLE: LDR Xn, Xm [, lsl 3]
H A DAArch64SchedNeoverseV2.td1354 def : InstRW<[V2Write_7cyc_1F_1L], (instregex "^LDR[SDQ]l$")>;
1362 (instregex "^LDR[BHSDQ](pre|post)$")>;
1365 def : InstRW<[V2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
1373 def : InstRW<[V2Write_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td377 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate
390 def : InstRW<[A57WriteLdrAm3], (instregex "LDR(H|SH|SB)$")>;
418 // --- LDR pre-indexed ---
437 (instregex "LDR(H|SH|SB)_PRE")>;
455 // --- LDR post-indexed ---
456 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackOne], (instregex "LDR(T?)_POST_IMM",
457 "LDRB(T?)_POST_IMM", "LDR(SB|H|SH)Ti", "t2LDRB_POST")>;
464 (instregex "LDR(H|SH|SB)_POST")>;
469 "LDRB_POST_REG", "LDR(B?)T_POST$")>;
483 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR(SB|H|SH)Tr")>;
H A DARMScheduleR52.td291 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
299 "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
301 "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
511 // LDRLIT pseudo instructions, they expand to LDR + PICADD
514 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
H A DARMScheduleSwift.td357 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
367 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
370 (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
540 // LDRLIT pseudo instructions, they expand to LDR + PICADD
543 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
H A DARMScheduleM4.td56 def : M4UnitL2I<(instregex "(t|t2)LDR")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFP.td46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
49 // For z13 we prefer LDR over LER to avoid partial register dependencies.
H A DSystemZInstrInfo.cpp973 Opcode = SystemZ::LDR; in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h255 LDR, enumerator
/freebsd/contrib/file/magic/Magdir/
H A Dintel91 >>>7 string LDR UNDI image
H A Dfilesystems446 >>>>>329 string Moved\ or\ missing\ IBMBIO.LDR\n\r
449 >>>>>>>>411 string Caldera\ Inc.\0 \b, DR-DOS MBR (IBMBIO.LDR)
665 # DOS names like NTLDR,CMLDR,$LDR$ are 8 right space padded bytes+3 bytes
1582 # loadernames are NTLDR,CMLDR,PELDR,$LDR$ or BOOTMGR

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