| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopDataPrefetch.cpp | 182 LoopDataPrefetch LDP(AC, DT, LI, SE, TTI, ORE); in run() local
183 bool Changed = LDP.run(); in run()
209 LoopDataPrefetch LDP(AC, DT, LI, SE, TTI, ORE); in runOnFunction() local
210 return LDP.run(); in runOnFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Schedule.td | 62 // LDP,LDPSW,LDNP,LDXP,LDAXP
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| H A D | AArch64FalkorHWPFFix.cpp | 130 FalkorMarkStridedAccesses LDP(LI, SE); in runOnFunction() local
131 return LDP.run(); in runOnFunction()
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| H A D | AArch64SchedTSV110.td | 455 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi], (instregex "^LDP(W|X)i$")>;
456 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi],(instregex "^LDP(W|X)(post|pre)$")>;
531 def : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt, WriteLDHi], (instregex "^LDP[DQS](post|pre)")>;
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| H A D | AArch64SchedFalkorDetails.td | 1106 (instregex "LDP(D|S)i$")>;
1108 (instregex "LDP(D|S)(pre|post)$")>;
1170 (instregex "^LDP(W|X)i$")>;
1172 (instregex "^LDP(W|X)(post|pre)$")>;
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| H A D | AArch64SchedA55.td | 266 def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)i")>;
270 def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)(pre|post)")>;
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| H A D | AArch64SchedExynosM4.td | 615 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
696 WriteAdr], (instregex "^LDP[SD]post")>;
702 WriteAdr], (instregex "^LDP[SD]pre")>;
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| H A D | AArch64SchedExynosM3.td | 520 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
583 WriteAdr], (instregex "^LDP[DS](post|pre)")>;
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| H A D | AArch64SchedAmpere1.td | 672 } // The second register of a load-pair: LDP,LDPSW,LDNP,LDXP,LDAXP
962 (instregex "(LDNP|LDP|LDPSW)(X|W)")>;
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| H A D | AArch64SchedAmpere1B.td | 628 } // The second register of a load-pair: LDP,LDPSW,LDNP,LDXP,LDAXP
944 (instregex "(LDNP|LDP|LDPSW)(X|W)")>;
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| H A D | AArch64SchedExynosM5.td | 672 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
752 WriteAdr], (instregex "^LDP[SD](post|pre)")>;
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| H A D | AArch64SchedThunderX3T110.td | 325 // Load vector pair, immed offset, Q-form [LDP/LDNP].
335 // Load vector pair, immed offset, S/D-form [LDP/LDNP].
873 // LDP only breaks into *one* LS micro-op. Thus
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| H A D | AArch64ISelLowering.h | 511 LDP, enumerator
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| H A D | AArch64SchedA510.td | 276 def : InstRW<[CortexA510WriteVLD1,CortexA510WriteLDP2], (instregex "LDP(X|D)i")>;
280 def : InstRW<[WriteAdr, CortexA510WriteVLD1,CortexA510WriteLDP2], (instregex "LDP(X|D)(pre|post)")>;
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| H A D | AArch64SchedCyclone.td | 271 // LDP high register write is fused with the load, but a nop micro-op remains.
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| H A D | AArch64SchedKryoDetails.td | 1420 (instregex "LDP(D|S)(post|pre)")>;
1432 (instregex "LDP(W|X)(post|pre)")>;
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| H A D | AArch64SchedNeoverseN1.td | 505 (instregex "^LDP[SD](pre|post)$")>;
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| H A D | AArch64SchedThunderX2T99.td | 613 // LDP only breaks into *one* LS micro-op. Thus
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| H A D | AArch64SchedNeoverseV1.td | 761 (instregex "^LDP[SD](pre|post)$")>;
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| H A D | AArch64SchedA64FX.td | 775 // LDP only breaks into *one* LS micro-op. Thus
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| H A D | AArch64SchedNeoverseN2.td | 887 (instregex "^LDP[SD](pre|post)$")>;
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| H A D | AArch64SchedNeoverseV2.td | 1384 (instregex "^LDP[SD](pre|post)$")>;
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap3-ldp.dts | 12 model = "TI OMAP3430 LDP (Zoom1 Labrador)";
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| /freebsd/contrib/sendmail/contrib/ |
| H A D | mail.local.linux | 157 MGD)7J"YY,3`*1LDP`LI**`*+5&-TG2*YLHK(3?P3"7KE!L@BQJ)+CD`/2`!>
|
| /freebsd/contrib/tcpdump/ |
| H A D | CHANGES | 34 LDP: Add missing fields of the Common Session Parameters TLV and fix the
396 CVE-2018-14461 (LDP)
1120 LDP over TCP
|