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Searched refs:IsRV64 (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZk.td86 let Predicates = [HasStdExtZknd, IsRV64] in {
91 } // Predicates = [HasStdExtZknd, IsRV64]
93 let Predicates = [HasStdExtZkndOrZkne, IsRV64] in {
97 } // Predicates = [HasStdExtZkndOrZkne, IsRV64]
104 let Predicates = [HasStdExtZkne, IsRV64] in {
107 } // Predicates = [HasStdExtZkne, IsRV64]
125 let Predicates = [HasStdExtZknh, IsRV64] in {
130 } // Predicates = [HasStdExtZknh, IsRV64]
156 let Predicates = [HasStdExtZknd, IsRV64] in {
160 } // Predicates = [HasStdExtZknd, IsRV64]
[all …]
H A DRISCVInstrInfoM.td54 let Predicates = [HasStdExtZmmul, IsRV64], IsSignExtendingOpW = 1 in {
57 } // Predicates = [HasStdExtZmmul, IsRV64]
59 let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
68 } // Predicates = [HasStdExtM, IsRV64]
89 let Predicates = [HasStdExtZmmul, IsRV64] in
92 let Predicates = [HasStdExtM, IsRV64] in {
112 } // Predicates = [HasStdExtM, IsRV64]
114 let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in {
121 } // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba]
H A DRISCVInstrInfoP.td126 let Predicates = [HasStdExtP, IsRV64] in {
132 } // Predicates = [HasStdExtP, IsRV64]
142 let Predicates = [HasStdExtP, IsRV64] in {
145 } // Predicates = [HasStdExtP, IsRV64]
149 let Predicates = [HasStdExtP, IsRV64] in
159 let Predicates = [HasStdExtP, IsRV64] in {
162 } // Predicates = [HasStdExtP, IsRV64]
166 let Predicates = [HasStdExtP, IsRV64] in
H A DRISCVInstrInfoA.td90 let Predicates = [HasStdExtZalrsc, IsRV64] in {
94 } // Predicates = [HasStdExtZalrsc, IsRV64]
96 let Predicates = [HasStdExtZaamo, IsRV64] in {
115 } // Predicates = [HasStdExtZaamo, IsRV64]
182 let Predicates = [HasAtomicLdSt, IsRV64] in {
229 defm : AMOPat<"atomic_swap_i64", "AMOSWAP_D", i64, [IsRV64]>;
230 defm : AMOPat<"atomic_load_add_i64", "AMOADD_D", i64, [IsRV64]>;
231 defm : AMOPat<"atomic_load_and_i64", "AMOAND_D", i64, [IsRV64]>;
232 defm : AMOPat<"atomic_load_or_i64", "AMOOR_D", i64, [IsRV64]>;
233 defm : AMOPat<"atomic_load_xor_i64", "AMOXOR_D", i64, [IsRV64]>;
[all …]
H A DRISCVInstrInfoZb.td289 let Predicates = [HasStdExtZba, IsRV64] in {
300 } // Predicates = [HasStdExtZba, IsRV64]
312 let Predicates = [HasStdExtZbbOrZbkb, IsRV64], IsSignExtendingOpW = 1 in {
320 } // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
364 let Predicates = [HasStdExtZbbOrP, IsRV64], IsSignExtendingOpW = 1 in
367 let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
372 } // Predicates = [HasStdExtZbb, IsRV64]
413 let Predicates = [HasStdExtZbkb, IsRV64], IsSignExtendingOpW = 1 in
422 let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
425 } // Predicates = [HasStdExtZbb, IsRV64]
[all …]
H A DRISCVGISel.td98 let Predicates = [IsRV64] in {
119 let Predicates = [HasAtomicLdSt, IsRV64] in {
135 let Predicates = [IsRV64] in {
150 let Predicates = [IsRV64, NotHasStdExtZba] in
157 let Predicates = [IsRV64, NoStdExtZbb, NoStdExtZbkb] in {
168 let Predicates = [IsRV64, NoStdExtZbb] in {
179 let Predicates = [HasStdExtZba, IsRV64] in {
185 let Predicates = [HasStdExtZbb, IsRV64] in
190 let Predicates = [HasStdExtZbb, IsRV64] in {
197 let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
H A DRISCVInstrInfoZalasr.td56 let Predicates = [HasStdExtZalasr, IsRV64] in {
59 } // Predicates = [HasStdExtZalasr, IsRV64]
101 } // Predicates = [HasStdExtZalasr, IsRV64]
103 let Predicates = [HasStdExtZalasr, IsRV64] in {
112 } // Predicates = [HasStdExtZalasr, IsRV64]
H A DRISCVInstrInfoD.td61 def ZdinxExt : ExtInfo<"_INX", "Zfinx", [HasStdExtZdinx, IsRV64],
158 "fcvt.l.d", [IsRV64]>,
162 "fcvt.lu.d", [IsRV64]>,
166 "fcvt.d.l", [IsRV64]>,
170 "fcvt.d.lu", [IsRV64]>,
174 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
178 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
209 let Predicates = [HasStdExtZdinx, IsRV64] in {
222 } // Predicates = [HasStdExtZdinx, IsRV64]
252 let Predicates = [HasStdExtZdinx, IsRV64] in {
[all …]
H A DRISCVInstrInfoXTHead.td285 let Predicates = [HasVendorXTHeadBb, IsRV64],
289 } // Predicates = [HasVendorXTHeadBb, IsRV64]
311 let Predicates = [HasVendorXTHeadMac, IsRV64], IsSignExtendingOpW = 1 in {
314 } // Predicates = [HasVendorXTHeadMac, IsRV64]
326 let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
413 let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
463 let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF, IsRV64] in {
470 let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD, IsRV64] in {
589 let Predicates = [HasVendorXTHeadBb, IsRV64] in {
599 } // Predicates = [HasVendorXTHeadBb, IsRV64]
[all …]
H A DRISCVInstrInfoC.td345 let Predicates = [HasStdExtZca, IsRV64] in
388 let Predicates = [HasStdExtZca, IsRV64] in
424 Predicates = [HasStdExtZca, IsRV64] in
481 let Predicates = [HasStdExtZca, IsRV64] in {
531 let Predicates = [HasStdExtZca, IsRV64] in
591 let Predicates = [HasStdExtZca, IsRV64] in
721 let Predicates = [HasStdExtZca, IsRV64] in {
875 let Predicates = [HasStdExtZca, IsRV64] in {
878 } // Predicates = [HasStdExtZca, IsRV64]
899 let Predicates = [HasStdExtZca, IsRV64] in {
[all …]
H A DRISCVInstrInfoZfh.td71 [HasStdExtZhinx, HasStdExtZdinx, IsRV64],
74 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64],
200 "fcvt.l.h", [IsRV64]>,
204 "fcvt.lu.h", [IsRV64]>,
208 "fcvt.h.l", [IsRV64]>,
212 "fcvt.h.lu", [IsRV64]>,
281 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
333 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
534 let Predicates = [HasStdExtZfh, IsRV64] in {
562 } // Predicates = [HasStdExtZfh, IsRV64]
[all …]
H A DRISCVInstrInfoQ.td123 Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>,
127 Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>,
133 [IsRV64]>,
139 [IsRV64]>,
H A DRISCVFrameLowering.cpp128 bool IsRV64 = STI.is64Bit(); in emitSCSPrologue() local
138 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
187 bool IsRV64 = STI.is64Bit(); in emitSCSEpilogue() local
192 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
746 bool IsRV64 = STI.is64Bit(); in allocateStack() local
759 BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in allocateStack()
778 BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in allocateStack()
798 BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in allocateStack()
836 BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in allocateStack()
1142 bool IsRV64 = STI.is64Bit(); in emitPrologue() local
[all …]
H A DRISCVInstrInfoZa.td66 let Predicates = [HasStdExtZacas, IsRV64] in {
69 } // Predicates = [HasStdExtZacas, IsRV64]
120 defm : AMOCASPat<"atomic_cmp_swap_i64", "AMOCAS_D_RV64", i64, [IsRV64]>;
H A DRISCVInstrInfoZc.td172 let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
311 let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
314 } // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
H A DRISCVInstrInfoF.td418 "fcvt.l.s", [IsRV64]>,
422 "fcvt.lu.s", [IsRV64]>,
426 "fcvt.s.l", [IsRV64]>,
430 "fcvt.s.lu", [IsRV64]>,
564 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
791 let Predicates = [HasStdExtF, IsRV64] in {
823 } // Predicates = [HasStdExtF, IsRV64]
825 let Predicates = [HasStdExtZfinx, IsRV64] in {
857 } // Predicates = [HasStdExtZfinx, IsRV64]
H A DRISCVInstrInfo.td876 let Predicates = [IsRV64] in {
906 } // Predicates = [IsRV64]
974 let Predicates = [IsRV64, HasStdExtH] in {
1023 let Predicates = [IsRV64] in {
1027 } // Predicates = [IsRV64]
1036 let Predicates = [IsRV64] in {
1039 } // Predicates = [IsRV64]
1180 let Predicates = [IsRV64] in {
1196 } // Predicates = [IsRV64]
1471 (SRAI (i64 (SLLI $rs, 63)), 63)>, Requires<[IsRV64]>;
[all …]
H A DRISCVInstrInfoXAndes.td632 let Predicates = [HasVendorXAndesPerf, IsRV64] in {
642 } // Predicates = [HasVendorXAndesPerf, IsRV64]
753 let Predicates = [HasVendorXAndesPerf, IsRV64] in {
768 } // Predicates = [HasVendorXAndesPerf, IsRV64]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp68 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
75 } else if (ABIName.starts_with("ilp32") && IsRV64) { in computeTargetABI()
79 } else if (ABIName.starts_with("lp64") && !IsRV64) { in computeTargetABI()
83 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E && in computeTargetABI()
89 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E && in computeTargetABI()
98 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && in computeTargetABI()
106 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
149 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
150 unsigned XLen = IsRV64 ? 64 : 32; in parseFeatureBits()
H A DRISCVMatInt.cpp55 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in generateInstSeqImpl() local
64 if (!IsRV64 && STI.hasFeature(RISCV::FeatureVendorXqcili)) { in generateInstSeqImpl()
98 if (IsRV64 && Hi20) { in generateInstSeqImpl()
111 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeqImpl()
540 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in getIntMatCost() local
542 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
H A DRISCVBaseInfo.h590 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
658 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) { in getStackAdjBase() argument
666 unsigned RegSize = IsRV64 ? 8 : 4; in getStackAdjBase()
H A DRISCVInstPrinter.cpp306 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in printStackAdj() local
309 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64); in printStackAdj()
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp79 bool parseCPU(StringRef CPU, bool IsRV64) { in parseCPU() argument
84 return Info->is64Bit() == IsRV64; in parseCPU()
87 bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) { in parseTuneCPU() argument
98 return parseCPU(TuneCPU, IsRV64); in parseTuneCPU()
108 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidCPUArchList() argument
110 if (IsRV64 == C.is64Bit()) in fillValidCPUArchList()
115 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidTuneCPUArchList() argument
117 if (IsRV64 == C.is64Bit()) in fillValidTuneCPUArchList()
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h57 LLVM_ABI bool parseCPU(StringRef CPU, bool IsRV64);
58 LLVM_ABI bool parseTuneCPU(StringRef CPU, bool IsRV64);
61 bool IsRV64);
63 bool IsRV64);
H A DRISCVISAInfo.h82 printEnabledExtensions(bool IsRV64, std::set<StringRef> &EnabledFeatureNames,

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