Home
last modified time | relevance | path

Searched refs:IsRV64 (Results 1 – 25 of 30) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZk.td87 let Predicates = [HasStdExtZknd, IsRV64] in {
92 } // Predicates = [HasStdExtZknd, IsRV64]
94 let Predicates = [HasStdExtZkndOrZkne, IsRV64] in {
98 } // Predicates = [HasStdExtZkndOrZkne, IsRV64]
105 let Predicates = [HasStdExtZkne, IsRV64] in {
108 } // Predicates = [HasStdExtZkne, IsRV64]
126 let Predicates = [HasStdExtZknh, IsRV64] in {
131 } // Predicates = [HasStdExtZknh, IsRV64]
157 let Predicates = [HasStdExtZknd, IsRV64] in {
161 } // Predicates = [HasStdExtZknd, IsRV64]
[all...]
H A DRISCVInstrInfoM.td49 let Predicates = [HasStdExtZmmul, IsRV64], IsSignExtendingOpW = 1 in {
52 } // Predicates = [HasStdExtZmmul, IsRV64]
54 let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
63 } // Predicates = [HasStdExtM, IsRV64]
84 let Predicates = [HasStdExtZmmul, IsRV64] in
87 let Predicates = [HasStdExtM, IsRV64] in {
107 } // Predicates = [HasStdExtM, IsRV64]
109 let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in {
116 } // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba]
122 let Predicates = [HasStdExtZmmul, IsRV64] in {
[all …]
H A DRISCVInstrInfoZb.td293 let Predicates = [HasStdExtZba, IsRV64] in {
304 } // Predicates = [HasStdExtZba, IsRV64]
316 let Predicates = [HasStdExtZbbOrZbkb, IsRV64], IsSignExtendingOpW = 1 in {
324 } // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
367 let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
374 } // Predicates = [HasStdExtZbb, IsRV64]
414 let Predicates = [HasStdExtZbkb, IsRV64], IsSignExtendingOpW = 1 in
423 let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
426 } // Predicates = [HasStdExtZbb, IsRV64]
433 let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
[all …]
H A DRISCVInstrInfoA.td90 let Predicates = [HasStdExtAOrZalrsc, IsRV64] in {
94 } // Predicates = [HasStdExtAOrZalrsc, IsRV64]
96 let Predicates = [HasStdExtAOrZaamo, IsRV64] in {
115 } // Predicates = [HasStdExtAOrZaamo, IsRV64]
134 let Predicates = [HasAtomicLdSt, IsRV64] in {
179 defm : AMOPat<"atomic_swap_i64", "AMOSWAP_D", i64, [IsRV64]>;
180 defm : AMOPat<"atomic_load_add_i64", "AMOADD_D", i64, [IsRV64]>;
181 defm : AMOPat<"atomic_load_and_i64", "AMOAND_D", i64, [IsRV64]>;
182 defm : AMOPat<"atomic_load_or_i64", "AMOOR_D", i64, [IsRV64]>;
183 defm : AMOPat<"atomic_load_xor_i64", "AMOXOR_D", i64, [IsRV64]>;
[all …]
H A DRISCVInstrInfoXVentana.td17 let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
31 let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
45 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]
H A DRISCVInstrInfoD.td61 def ZdinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZdinx, IsRV64],
156 "fcvt.l.d", [IsRV64]>,
160 "fcvt.lu.d", [IsRV64]>,
164 "fcvt.d.l", [IsRV64]>,
168 "fcvt.d.lu", [IsRV64]>,
172 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
176 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
207 let Predicates = [HasStdExtZdinx, IsRV64] in {
219 } // Predicates = [HasStdExtZdinx, IsRV64]
248 let Predicates = [HasStdExtZdinx, IsRV64] in {
[all …]
H A DRISCVInstrInfoXTHead.td112 let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
266 let Predicates = [HasVendorXTHeadBb, IsRV64], IsSignExtendingOpW = 1 in {
269 } // Predicates = [HasVendorXTHeadBb, IsRV64]
291 let Predicates = [HasVendorXTHeadMac, IsRV64], IsSignExtendingOpW = 1 in {
294 } // Predicates = [HasVendorXTHeadMac, IsRV64]
306 let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
393 let Predicates = [HasVendorXTHeadMemIdx, IsRV64], DecoderNamespace = "XTHeadMemIdx" in {
445 let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF, IsRV64],
453 let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD, IsRV64],
577 let Predicates = [HasVendorXTHeadBb, IsRV64] in {
[all …]
H A DRISCVInstrInfoZfh.td57 [HasStdExtZhinx, HasStdExtZdinx, IsRV64],
60 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64],
173 "fcvt.l.h", [IsRV64]>,
177 "fcvt.lu.h", [IsRV64]>,
181 "fcvt.h.l", [IsRV64]>,
185 "fcvt.h.lu", [IsRV64]>,
254 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
304 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
504 let Predicates = [HasStdExtZfh, IsRV64] in {
532 } // Predicates = [HasStdExtZfh, IsRV64]
[all …]
H A DRISCVInstrInfoC.td344 let Predicates = [HasStdExtCOrZca, IsRV64] in
378 let Predicates = [HasStdExtCOrZca, IsRV64] in
418 Predicates = [HasStdExtCOrZca, IsRV64] in
480 let Predicates = [HasStdExtCOrZca, IsRV64] in {
528 let Predicates = [HasStdExtCOrZca, IsRV64] in
586 let Predicates = [HasStdExtCOrZca, IsRV64] in
723 let Predicates = [HasStdExtCOrZca, IsRV64] in {
879 let Predicates = [HasStdExtCOrZca, IsRV64] in {
882 } // Predicates = [HasStdExtCOrZca, IsRV64]
899 let Predicates = [HasStdExtCOrZca, IsRV64] in {
[all …]
H A DRISCVInstrInfoZalasr.td56 let Predicates = [HasStdExtZalasr, IsRV64] in {
59 } // Predicates = [HasStdExtZalasr, IsRV64]
H A DRISCVInstrInfoZa.td66 let Predicates = [HasStdExtZacas, IsRV64] in {
69 } // Predicates = [HasStdExtZacas, IsRV64]
120 defm : AMOCASPat<"atomic_cmp_swap_i64", "AMOCAS_D_RV64", i64, [IsRV64]>;
H A DRISCVInstrInfoF.td369 "fcvt.l.s", [IsRV64]>,
373 "fcvt.lu.s", [IsRV64]>,
377 "fcvt.s.l", [IsRV64]>,
381 "fcvt.s.lu", [IsRV64]>,
513 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
735 let Predicates = [HasStdExtF, IsRV64] in {
767 } // Predicates = [HasStdExtF, IsRV64]
769 let Predicates = [HasStdExtZfinx, IsRV64] in {
801 } // Predicates = [HasStdExtZfinx, IsRV64]
H A DRISCVInstrInfoZc.td169 let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
300 let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
303 } // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
H A DRISCVInstrInfo.td750 let Predicates = [IsRV64] in {
777 } // Predicates = [IsRV64]
837 let Predicates = [IsRV64, HasStdExtH] in {
880 let Predicates = [IsRV64] in {
884 } // Predicates = [IsRV64]
891 let Predicates = [IsRV64] in {
894 } // Predicates = [IsRV64]
1035 let Predicates = [IsRV64] in {
1051 } // Predicates = [IsRV64]
1689 let Predicates = [IsRV64], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
[all …]
H A DRISCVSubtarget.h165 bool is64Bit() const { return IsRV64; } in is64Bit()
H A DRISCVFrameLowering.cpp83 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue() local
93 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
143 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSEpilogue() local
148 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp41 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
48 } else if (ABIName.starts_with("ilp32") && IsRV64) { in computeTargetABI()
52 } else if (ABIName.starts_with("lp64") && !IsRV64) { in computeTargetABI()
56 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E && in computeTargetABI()
62 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E && in computeTargetABI()
71 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && in computeTargetABI()
79 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
122 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
123 unsigned XLen = IsRV64 ? 64 : 32; in parseFeatureBits()
H A DRISCVBaseInfo.h481 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
542 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) { in getStackAdjBase() argument
545 if (!IsRV64) { in getStackAdjBase()
591 int64_t StackAdjustment, bool IsRV64) { in getSpimm() argument
594 unsigned StackAdjBase = getStackAdjBase(RlistVal, IsRV64); in getSpimm()
H A DRISCVMatInt.cpp51 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in generateInstSeqImpl() local
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
81 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeqImpl()
503 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in getIntMatCost() local
506 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
H A DRISCVInstPrinter.cpp283 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in printStackAdj() local
287 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64); in printStackAdj()
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp63 bool parseCPU(StringRef CPU, bool IsRV64) { in parseCPU() argument
68 return Info->is64Bit() == IsRV64; in parseCPU()
71 bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) { in parseTuneCPU() argument
82 return parseCPU(TuneCPU, IsRV64); in parseTuneCPU()
92 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidCPUArchList() argument
94 if (IsRV64 == C.is64Bit()) in fillValidCPUArchList()
99 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidTuneCPUArchList() argument
101 if (IsRV64 == C.is64Bit()) in fillValidTuneCPUArchList()
H A DRISCVISAInfo.cpp119 bool IsRV64, std::set<StringRef> &EnabledFeatureNames, in printEnabledExtensions() argument
152 unsigned XLen = IsRV64 ? 64 : 32; in printEnabledExtensions()
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h41 bool parseCPU(StringRef CPU, bool IsRV64);
42 bool parseTuneCPU(StringRef CPU, bool IsRV64);
44 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
45 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
H A DRISCVISAInfo.h79 static void printEnabledExtensions(bool IsRV64,
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DRISCVToolchain.cpp167 bool IsRV64 = ToolChain.getArch() == llvm::Triple::riscv64; in ConstructJob() local
169 if (IsRV64) { in ConstructJob()

12