1*0fca6ea1SDimitry Andric//===-- RISCVInstrInfoZalasr.td ---------------------------*- tablegen -*-===// 2*0fca6ea1SDimitry Andric// 3*0fca6ea1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0fca6ea1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0fca6ea1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0fca6ea1SDimitry Andric// 7*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 8*0fca6ea1SDimitry Andric// 9*0fca6ea1SDimitry Andric// This file describes the RISC-V instructions from the Zalasr (Load-Acquire 10*0fca6ea1SDimitry Andric// and Store-Release) extension 11*0fca6ea1SDimitry Andric// 12*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 13*0fca6ea1SDimitry Andric 14*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 15*0fca6ea1SDimitry Andric// Instruction class templates 16*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 17*0fca6ea1SDimitry Andric 18*0fca6ea1SDimitry Andriclet hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 19*0fca6ea1SDimitry Andricclass LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr> 20*0fca6ea1SDimitry Andric : RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO, 21*0fca6ea1SDimitry Andric (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1), 22*0fca6ea1SDimitry Andric opcodestr, "$rd, $rs1"> { 23*0fca6ea1SDimitry Andric let rs2 = 0; 24*0fca6ea1SDimitry Andric} 25*0fca6ea1SDimitry Andric 26*0fca6ea1SDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 27*0fca6ea1SDimitry Andricclass SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr> 28*0fca6ea1SDimitry Andric : RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO, 29*0fca6ea1SDimitry Andric (outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2), 30*0fca6ea1SDimitry Andric opcodestr, "$rs2, $rs1"> { 31*0fca6ea1SDimitry Andric let rd = 0; 32*0fca6ea1SDimitry Andric} 33*0fca6ea1SDimitry Andricmulticlass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> { 34*0fca6ea1SDimitry Andric def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">; 35*0fca6ea1SDimitry Andric def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">; 36*0fca6ea1SDimitry Andric} 37*0fca6ea1SDimitry Andric 38*0fca6ea1SDimitry Andricmulticlass SRL_r_aq_rl<bits<3> funct3, string opcodestr> { 39*0fca6ea1SDimitry Andric def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">; 40*0fca6ea1SDimitry Andric def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">; 41*0fca6ea1SDimitry Andric} 42*0fca6ea1SDimitry Andric 43*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 44*0fca6ea1SDimitry Andric// Instructions 45*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 46*0fca6ea1SDimitry Andric 47*0fca6ea1SDimitry Andriclet Predicates = [HasStdExtZalasr] in { 48*0fca6ea1SDimitry Andricdefm LB : LAQ_r_aq_rl<0b000, "lb">; 49*0fca6ea1SDimitry Andricdefm LH : LAQ_r_aq_rl<0b001, "lh">; 50*0fca6ea1SDimitry Andricdefm LW : LAQ_r_aq_rl<0b010, "lw">; 51*0fca6ea1SDimitry Andricdefm SB : SRL_r_aq_rl<0b000, "sb">; 52*0fca6ea1SDimitry Andricdefm SH : SRL_r_aq_rl<0b001, "sh">; 53*0fca6ea1SDimitry Andricdefm SW : SRL_r_aq_rl<0b010, "sw">; 54*0fca6ea1SDimitry Andric} // Predicates = [HasStdExtZalasr] 55*0fca6ea1SDimitry Andric 56*0fca6ea1SDimitry Andriclet Predicates = [HasStdExtZalasr, IsRV64] in { 57*0fca6ea1SDimitry Andricdefm LD : LAQ_r_aq_rl<0b011, "ld">; 58*0fca6ea1SDimitry Andricdefm SD : SRL_r_aq_rl<0b011, "sd">; 59*0fca6ea1SDimitry Andric} // Predicates = [HasStdExtZalasr, IsRV64] 60