| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1162 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1200 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1549 MVT IntermediateVT; in computeRegisterProperties() local
1552 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1617 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1632 IntermediateVT = RegisterEVT; in getVectorTypeBreakdown()
1663 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1664 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1688 IntermediateVT = NewVT; in getVectorTypeBreakdown()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 352 EVT IntermediateVT; in getCopyFromPartsVector() local
359 *DAG.getContext(), *CallConv, ValueVT, IntermediateVT, in getCopyFromPartsVector()
363 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, in getCopyFromPartsVector()
380 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, PartVT, IntermediateVT, in getCopyFromPartsVector()
390 IntermediateVT, V, InChain, CallConv); in getCopyFromPartsVector()
396 IntermediateVT.isVector() in getCopyFromPartsVector()
398 *DAG.getContext(), IntermediateVT.getScalarType(), in getCopyFromPartsVector()
399 IntermediateVT.getVectorElementCount() * NumParts) in getCopyFromPartsVector()
401 IntermediateVT.getScalarType(), in getCopyFromPartsVector()
403 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
[all …]
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| H A D | SelectionDAG.cpp | 2714 EVT IntermediateVT; in getReducedAlign() local
2717 TLI->getVectorTypeBreakdown(*getContext(), VT, IntermediateVT, in getReducedAlign()
2719 Ty = IntermediateVT.getTypeForEVT(*getContext()); in getReducedAlign()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 176 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
185 IntermediateVT = MVT::i1; in getVectorTypeBreakdownForCallingConv()
194 IntermediateVT = MVT::v32i1; in getVectorTypeBreakdownForCallingConv()
204 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT, in getVectorTypeBreakdownForCallingConv()
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| H A D | X86ISelLowering.h | 1624 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 309 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | MipsISelLowering.cpp | 123 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
126 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
127 RegisterVT = IntermediateVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
131 IntermediateVT = VT.getVectorElementType(); in getVectorTypeBreakdownForCallingConv()
133 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
134 return NumIntermediates * getNumRegisters(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 94 EVT &IntermediateVT,
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| H A D | RISCVISelLowering.cpp | 2421 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
2424 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 161 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
172 IntermediateVT = MVT::v8i1; in getVectorTypeBreakdownForCallingConv()
181 IntermediateVT = MVT::v64i1; in getVectorTypeBreakdownForCallingConv()
191 IntermediateVT = MVT::v128i1; in getVectorTypeBreakdownForCallingConv()
197 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| H A D | HexagonISelLowering.h | 271 EVT &IntermediateVT,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | SIISelLowering.cpp | 1126 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
1138 IntermediateVT = MVT::v2bf16; in getVectorTypeBreakdownForCallingConv()
1141 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1149 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1157 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1164 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1171 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1178 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1199 EVT &IntermediateVT,
1207 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
1209 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 535 EVT &IntermediateVT,
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| H A D | AArch64ISelLowering.cpp | 30498 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
30501 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
30507 assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!"); in getVectorTypeBreakdownForCallingConv()
30518 IntermediateVT = NewVT; in getVectorTypeBreakdownForCallingConv()
30535 IntermediateVT = RegisterVT = MVT::v16i8; in getVectorTypeBreakdownForCallingConv()
30538 IntermediateVT = RegisterVT = MVT::v8i16; in getVectorTypeBreakdownForCallingConv()
30541 IntermediateVT = RegisterVT = MVT::v4i32; in getVectorTypeBreakdownForCallingConv()
30544 IntermediateVT = RegisterVT = MVT::v2i64; in getVectorTypeBreakdownForCallingConv()
30547 IntermediateVT = RegisterVT = MVT::v8f16; in getVectorTypeBreakdownForCallingConv()
30550 IntermediateVT = RegisterVT = MVT::v4f32; in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8775 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector() local
8796 Arrange = DAG.getBitcast(IntermediateVT, Arrange); in LowerINT_TO_FPVector()
8800 IntermediateVT.getVectorNumElements()); in LowerINT_TO_FPVector()
8802 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, in LowerINT_TO_FPVector()
8805 Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange); in LowerINT_TO_FPVector()
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