| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1063 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1101 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1450 MVT IntermediateVT; in computeRegisterProperties() local
1453 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1518 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1533 IntermediateVT = RegisterEVT; in getVectorTypeBreakdown()
1564 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1565 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1589 IntermediateVT = NewVT; in getVectorTypeBreakdown()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 355 EVT IntermediateVT; in getCopyFromPartsVector() local
362 *DAG.getContext(), *CallConv, ValueVT, IntermediateVT, in getCopyFromPartsVector()
366 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, in getCopyFromPartsVector()
383 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, PartVT, IntermediateVT, in getCopyFromPartsVector()
393 IntermediateVT, V, InChain, CallConv); in getCopyFromPartsVector()
399 IntermediateVT.isVector() in getCopyFromPartsVector()
401 *DAG.getContext(), IntermediateVT.getScalarType(), in getCopyFromPartsVector()
402 IntermediateVT.getVectorElementCount() * NumParts) in getCopyFromPartsVector()
404 IntermediateVT.getScalarType(), in getCopyFromPartsVector()
406 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
[all …]
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| H A D | SelectionDAG.cpp | 2476 EVT IntermediateVT; in getReducedAlign() local
2479 TLI->getVectorTypeBreakdown(*getContext(), VT, IntermediateVT, in getReducedAlign()
2481 Ty = IntermediateVT.getTypeForEVT(*getContext()); in getReducedAlign()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 173 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
182 IntermediateVT = MVT::i1; in getVectorTypeBreakdownForCallingConv()
191 IntermediateVT = MVT::v32i1; in getVectorTypeBreakdownForCallingConv()
200 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT, in getVectorTypeBreakdownForCallingConv()
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| H A D | X86ISelLowering.h | 1537 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 307 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | MipsISelLowering.cpp | 125 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
128 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
129 RegisterVT = IntermediateVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
133 IntermediateVT = VT.getVectorElementType(); in getVectorTypeBreakdownForCallingConv()
135 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
136 return NumIntermediates * getNumRegisters(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | SIISelLowering.cpp | 1061 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
1073 IntermediateVT = MVT::v2bf16; in getVectorTypeBreakdownForCallingConv()
1076 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1084 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1092 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1100 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1107 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1114 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1172 EVT &IntermediateVT,
1180 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
1182 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 548 EVT &IntermediateVT,
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| H A D | RISCVISelLowering.cpp | 2368 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
2371 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
2373 if (RV64LegalI32 && Subtarget.is64Bit() && IntermediateVT == MVT::i32) in getVectorTypeBreakdownForCallingConv()
2374 IntermediateVT = MVT::i64; in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1019 EVT &IntermediateVT,
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| H A D | AArch64ISelLowering.cpp | 28651 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
28654 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
28660 assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!"); in getVectorTypeBreakdownForCallingConv()
28671 IntermediateVT = NewVT; in getVectorTypeBreakdownForCallingConv()
28688 IntermediateVT = RegisterVT = MVT::v16i8; in getVectorTypeBreakdownForCallingConv()
28691 IntermediateVT = RegisterVT = MVT::v8i16; in getVectorTypeBreakdownForCallingConv()
28694 IntermediateVT = RegisterVT = MVT::v4i32; in getVectorTypeBreakdownForCallingConv()
28697 IntermediateVT = RegisterVT = MVT::v2i64; in getVectorTypeBreakdownForCallingConv()
28700 IntermediateVT = RegisterVT = MVT::v8f16; in getVectorTypeBreakdownForCallingConv()
28703 IntermediateVT = RegisterVT = MVT::v4f32; in getVectorTypeBreakdownForCallingConv()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8731 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector() local
8752 Arrange = DAG.getBitcast(IntermediateVT, Arrange); in LowerINT_TO_FPVector()
8756 IntermediateVT.getVectorNumElements()); in LowerINT_TO_FPVector()
8758 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, in LowerINT_TO_FPVector()
8761 Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange); in LowerINT_TO_FPVector()
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