| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMapAsm2IntrinV62.gen.td | 9 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
16 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
24 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
31 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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| H A D | HexagonIntrinsicsV60.td | 84 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
90 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
91 def: Pat<(IntID HvxVR:$src1),
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
98 multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
99 def: Pat<(IntID HvxWR:$src1),
102 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
106 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
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| H A D | HexagonIntrinsics.td | 11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
12 : Pat <(IntID I32:$Rs),
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
16 : Pat <(IntID I32:$Rs, I32:$Rt),
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
20 : Pat <(IntID I32:$Rs, I64:$Rt),
143 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
186 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
187 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
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| H A D | HexagonOptimizeSZextends.cpp | 40 bool intrinsicAlreadySextended(Intrinsic::ID IntID);
49 bool HexagonOptimizeSZextends::intrinsicAlreadySextended(Intrinsic::ID IntID) { in intrinsicAlreadySextended() argument
50 switch(IntID) { in intrinsicAlreadySextended()
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| H A D | HexagonISelLowering.cpp | 3905 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked in emitLoadLinked() local
3909 Builder.CreateIntrinsic(IntID, Addr, /*FMFSource=*/nullptr, "larx"); in emitLoadLinked()
3926 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked in emitStoreConditional() local
3931 Value *Call = Builder.CreateIntrinsic(IntID, {Addr, Val}, in emitStoreConditional()
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| H A D | HexagonVectorCombine.cpp | 144 Value *createHvxIntrinsic(IRBuilderBase &Builder, Intrinsic::ID IntID,
2570 Intrinsic::ID IntID, Type *RetTy, in createHvxIntrinsic() argument
2598 Intrinsic::getOrInsertDeclaration(F.getParent(), IntID, ArgTys); in createHvxIntrinsic()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | Hexagon.cpp | 83 auto MakeCircOp = [this, E](unsigned IntID, bool IsLoad) { in EmitHexagonBuiltinExpr() argument
100 llvm::Value *Result = Builder.CreateCall(CGM.getIntrinsic(IntID), Ops); in EmitHexagonBuiltinExpr()
117 auto MakeBrevLd = [this, E](unsigned IntID, llvm::Type *DestTy) { in EmitHexagonBuiltinExpr() argument
134 CGM.getIntrinsic(IntID), {BaseAddress, EmitScalarExpr(E->getArg(2))}); in EmitHexagonBuiltinExpr()
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| H A D | ARM.cpp | 2471 llvm::Type *ResTy, unsigned IntID, in packTBLDVectorList() argument
2503 TblF = CGF.CGM.getIntrinsic(IntID, ResTy); in packTBLDVectorList()
3888 unsigned IntID; in EmitSVEPredicateCast() local
3897 IntID = Intrinsic::aarch64_sve_convert_from_svbool; in EmitSVEPredicateCast()
3901 IntID = Intrinsic::aarch64_sve_convert_to_svbool; in EmitSVEPredicateCast()
3906 Function *F = CGM.getIntrinsic(IntID, IntrinsicTy); in EmitSVEPredicateCast()
3930 unsigned IntID) { in EmitSVEGatherLoad() argument
3940 F = CGM.getIntrinsic(IntID, {OverloadedTy, Ops[1]->getType()}); in EmitSVEGatherLoad()
3946 F = CGM.getIntrinsic(IntID, OverloadedTy); in EmitSVEGatherLoad()
3984 unsigned IntID) { in EmitSVEScatterStore() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/ |
| H A D | ARCRuntimeEntryPoints.h | 146 Function *getIntrinsicEntryPoint(Function *&Decl, Intrinsic::ID IntID) { in getIntrinsicEntryPoint() argument
150 return Decl = Intrinsic::getOrInsertDeclaration(TheModule, IntID); in getIntrinsicEntryPoint()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Function.cpp | 506 if (IntID) { in Function()
510 if (!Intrinsic::getIntrinsicSignature(IntID, Ty, OverloadTys)) in Function()
513 setAttributes(Intrinsic::getAttributes(getContext(), IntID, Ty)); in Function()
932 return Intrinsic::isTargetIntrinsic(IntID); in isTargetIntrinsic()
940 IntID = Intrinsic::not_intrinsic; in updateAfterNameChange()
944 IntID = Intrinsic::lookupIntrinsicID(Name); in updateAfterNameChange()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrAltivec.td | 268 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
271 [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
275 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
279 [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;
283 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
288 (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;
291 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
294 [(set Ty:$VD, (IntID Ty:$VA, Ty:$VB))]>;
298 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
302 [(set OutTy:$VD, (IntID InTy:$VA, InTy:$VB))]>;
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| H A D | PPCISelDAGToDAG.cpp | 5349 auto IntID = N->getConstantOperandVal(0); in Select() local
5350 if (IntID == Intrinsic::ppc_fsels) { in Select()
5356 if (IntID == Intrinsic::ppc_bcdadd_p || IntID == Intrinsic::ppc_bcdsub_p) { in Select()
5359 IntID == Intrinsic::ppc_bcdadd_p ? PPC::BCDADD_rec : PPC::BCDSUB_rec; in Select()
5436 switch (IntID) { in Select()
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| H A D | PPCISelLowering.cpp | 12769 Intrinsic::ID IntID; in emitLoadLinked() local
12774 IntID = Intrinsic::ppc_lbarx; in emitLoadLinked()
12778 IntID = Intrinsic::ppc_lharx; in emitLoadLinked()
12782 IntID = Intrinsic::ppc_lwarx; in emitLoadLinked()
12785 IntID = Intrinsic::ppc_ldarx; in emitLoadLinked()
12789 Builder.CreateIntrinsic(IntID, Addr, /*FMFSource=*/nullptr, "larx"); in emitLoadLinked()
12804 Intrinsic::ID IntID; in emitStoreConditional() local
12809 IntID = Intrinsic::ppc_stbcx; in emitStoreConditional()
12813 IntID = Intrinsic::ppc_sthcx; in emitStoreConditional()
12817 IntID = Intrinsic::ppc_stwcx; in emitStoreConditional()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGObjC.cpp | 2203 static llvm::Function *getARCIntrinsic(llvm::Intrinsic::ID IntID, in getARCIntrinsic() argument
2205 llvm::Function *fn = CGM.getIntrinsic(IntID); in getARCIntrinsic()
2215 llvm::Function *&fn, llvm::Intrinsic::ID IntID, in emitARCValueOperation() argument
2221 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCValueOperation()
2239 llvm::Intrinsic::ID IntID) { in emitARCLoadOperation() argument
2241 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCLoadOperation()
2251 llvm::Intrinsic::ID IntID, in emitARCStoreOperation() argument
2256 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCStoreOperation()
2274 llvm::Intrinsic::ID IntID) { in emitARCCopyOperation() argument
2278 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCCopyOperation()
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| H A D | CodeGenFunction.h | 4804 unsigned IntID);
4807 unsigned IntID);
4819 unsigned IntID);
4822 unsigned IntID);
4825 unsigned IntID);
4830 unsigned IntID);
4833 unsigned IntID);
4836 unsigned IntID);
4839 unsigned IntID);
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | GlobalValue.h | 175 Intrinsic::ID IntID = (Intrinsic::ID)0U;
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| H A D | Function.h | 244 Intrinsic::ID getIntrinsicID() const LLVM_READONLY { return IntID; } in getIntrinsicID()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5744 SDValue IntID = in lowerVECTOR_SHUFFLE() local
5747 IntID, in lowerVECTOR_SHUFFLE()
10909 SDValue IntID = DAG.getTargetConstant(VlsegInts[NF - 2], DL, XLenVT); in LowerINTRINSIC_W_CHAIN() local
10915 IntID, in LowerINTRINSIC_W_CHAIN()
11006 SDValue IntID = DAG.getTargetConstant(VssegInts[NF - 2], DL, XLenVT); in LowerINTRINSIC_VOID() local
11021 IntID, in LowerINTRINSIC_VOID()
12444 SDValue IntID = DAG.getTargetConstant( in lowerFixedLengthVectorLoadToRVV() local
12446 SmallVector<SDValue, 4> Ops{Load->getChain(), IntID}; in lowerFixedLengthVectorLoadToRVV()
12502 SDValue IntID = DAG.getTargetConstant( in lowerFixedLengthVectorStoreToRVV() local
12506 {Store->getChain(), IntID, NewValue, Store->getBasePtr(), VL}, in lowerFixedLengthVectorStoreToRVV()
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| H A D | RISCVISelDAGToDAG.cpp | 100 SDValue IntID = in PreprocessISelDAG() local
103 IntID, in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2623 Intrinsic::ID IntID = in computeKnownBitsForTargetNode() local
2625 switch (IntID) { in computeKnownBitsForTargetNode()
27849 Intrinsic::ID IntID = in ReplaceNodeResults() local
27851 switch (IntID) { in ReplaceNodeResults()
29585 Intrinsic::ID IntID; in LowerVECTOR_DEINTERLEAVE() local
29590 IntID = Intrinsic::aarch64_sve_uzp_x2; in LowerVECTOR_DEINTERLEAVE()
29596 IntID = Intrinsic::aarch64_sve_uzp_x4; in LowerVECTOR_DEINTERLEAVE()
29601 Ops.push_back(DAG.getTargetConstant(IntID, DL, MVT::i64)); in LowerVECTOR_DEINTERLEAVE()
29626 Intrinsic::ID IntID; in LowerVECTOR_INTERLEAVE() local
29631 IntID = Intrinsic::aarch64_sve_zip_x2; in LowerVECTOR_INTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4584 SDValue IntID = HG->getIntID(); in SplitVecOp_VECTOR_HISTOGRAM() local
4592 SDValue OpsLo[] = {HG->getChain(), Inc, MaskLo, Ptr, IndexLo, Scale, IntID}; in SplitVecOp_VECTOR_HISTOGRAM()
4595 SDValue OpsHi[] = {Lo, Inc, MaskHi, Ptr, IndexHi, Scale, IntID}; in SplitVecOp_VECTOR_HISTOGRAM()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 20046 Intrinsic::ID IntID = in computeKnownBitsForTargetNode() local
20048 switch (IntID) { in computeKnownBitsForTargetNode()
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| /freebsd/sys/contrib/dev/acpica/ |
| H A D | changes.txt | 231 simulates an interrupt with a IntID (GSIV) equal to the first argument of
233 execute the _EVT method of the GED device associated with that IntID.
|