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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td9 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
16 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
24 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
31 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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H A DHexagonIntrinsicsV60.td84 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
90 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
91 def: Pat<(IntID HvxVR:$src1),
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
98 multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
99 def: Pat<(IntID HvxWR:$src1),
102 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
106 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
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H A DHexagonIntrinsics.td11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
12 : Pat <(IntID I32:$Rs),
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
16 : Pat <(IntID I32:$Rs, I32:$Rt),
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
20 : Pat <(IntID I32:$Rs, I64:$Rt),
143 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
186 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
187 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
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H A DHexagonOptimizeSZextends.cpp47 bool intrinsicAlreadySextended(Intrinsic::ID IntID);
56 bool HexagonOptimizeSZextends::intrinsicAlreadySextended(Intrinsic::ID IntID) { in intrinsicAlreadySextended() argument
57 switch(IntID) { in intrinsicAlreadySextended()
H A DHexagonISelLowering.cpp3870 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked in emitLoadLinked()
3872 Function *Fn = Intrinsic::getDeclaration(M, IntID); in emitLoadLinked()
3891 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked in emitStoreConditional()
3893 Function *Fn = Intrinsic::getDeclaration(M, IntID); in emitStoreConditional()
3866 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked emitLoadLinked() local
3887 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked emitStoreConditional() local
H A DHexagonVectorCombine.cpp143 Value *createHvxIntrinsic(IRBuilderBase &Builder, Intrinsic::ID IntID,
2569 Intrinsic::ID IntID, Type *RetTy, in createHvxIntrinsic() argument
2597 Function *IntrFn = Intrinsic::getDeclaration(F.getParent(), IntID, ArgTys); in createHvxIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/
H A DARCRuntimeEntryPoints.h138 Function *getIntrinsicEntryPoint(Function *&Decl, Intrinsic::ID IntID) { in getIntrinsicEntryPoint() argument
142 return Decl = Intrinsic::getDeclaration(TheModule, IntID); in getIntrinsicEntryPoint()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td268 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
271 [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
275 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
279 [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;
283 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
288 (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;
291 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
294 [(set Ty:$VD, (IntID Ty:$VA, Ty:$VB))]>;
298 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
302 [(set OutTy:$VD, (IntID InTy:$VA, InTy:$VB))]>;
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H A DPPCISelDAGToDAG.cpp5335 auto IntID = N->getConstantOperandVal(0); in Select() local
5336 if (IntID == Intrinsic::ppc_fsels) { in Select()
5342 if (IntID == Intrinsic::ppc_bcdadd_p || IntID == Intrinsic::ppc_bcdsub_p) { in Select()
5345 IntID == Intrinsic::ppc_bcdadd_p ? PPC::BCDADD_rec : PPC::BCDSUB_rec; in Select()
5422 switch (IntID) { in Select()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGObjC.cpp2158 static llvm::Function *getARCIntrinsic(llvm::Intrinsic::ID IntID, in getARCIntrinsic() argument
2160 llvm::Function *fn = CGM.getIntrinsic(IntID); in getARCIntrinsic()
2170 llvm::Function *&fn, llvm::Intrinsic::ID IntID, in emitARCValueOperation() argument
2176 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCValueOperation()
2194 llvm::Intrinsic::ID IntID) { in emitARCLoadOperation() argument
2196 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCLoadOperation()
2206 llvm::Intrinsic::ID IntID, in emitARCStoreOperation() argument
2211 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCStoreOperation()
2229 llvm::Intrinsic::ID IntID) { in emitARCCopyOperation() argument
2233 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCCopyOperation()
H A DCodeGenFunction.h4632 unsigned IntID);
4635 unsigned IntID);
4647 unsigned IntID);
4650 unsigned IntID);
4653 unsigned IntID);
4664 unsigned IntID);
4667 unsigned IntID);
4670 unsigned IntID);
4673 unsigned IntID);
H A DCGBuiltin.cpp8381 llvm::Type *ResTy, unsigned IntID, in packTBLDVectorList() argument
8413 TblF = CGF.CGM.getIntrinsic(IntID, ResTy); in packTBLDVectorList()
9811 unsigned IntID; in EmitSVEPredicateCast() local
9820 IntID = Intrinsic::aarch64_sve_convert_from_svbool; in EmitSVEPredicateCast()
9824 IntID = Intrinsic::aarch64_sve_convert_to_svbool; in EmitSVEPredicateCast()
9829 Function *F = CGM.getIntrinsic(IntID, IntrinsicTy); in EmitSVEPredicateCast()
9837 unsigned IntID) { in EmitSVEGatherLoad() argument
9847 F = CGM.getIntrinsic(IntID, {OverloadedTy, Ops[1]->getType()}); in EmitSVEGatherLoad()
9853 F = CGM.getIntrinsic(IntID, OverloadedTy); in EmitSVEGatherLoad()
9891 unsigned IntID) { in EmitSVEScatterStore() argument
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/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DFunction.cpp507 if (IntID) in Function()
508 setAttributes(Intrinsic::getAttributes(getContext(), IntID)); in Function()
932 return isTargetIntrinsic(IntID); in isTargetIntrinsic()
981 IntID = Intrinsic::not_intrinsic; in updateAfterNameChange()
985 IntID = lookupIntrinsicID(Name); in updateAfterNameChange()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DGlobalValue.h173 Intrinsic::ID IntID = (Intrinsic::ID)0U;
H A DFunction.h242 Intrinsic::ID getIntrinsicID() const LLVM_READONLY { return IntID; } in getIntrinsicID()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5138 SDValue IntID = in lowerVECTOR_SHUFFLE()
5141 IntID, in lowerVECTOR_SHUFFLE()
9454 SDValue IntID = DAG.getTargetConstant( in LowerINTRINSIC_W_CHAIN()
9458 SmallVector<SDValue, 8> Ops{Load->getChain(), IntID}; in LowerINTRINSIC_W_CHAIN()
9505 SDValue IntID = DAG.getTargetConstant(VlsegInts[NF - 2], DL, XLenVT); in LowerINTRINSIC_W_CHAIN()
9510 SmallVector<SDValue, 12> Ops = {Load->getChain(), IntID}; in LowerINTRINSIC_W_CHAIN()
9587 SDValue IntID = DAG.getTargetConstant( in LowerINTRINSIC_VOID()
9592 SmallVector<SDValue, 8> Ops{Store->getChain(), IntID}; in LowerINTRINSIC_VOID()
9626 SDValue IntID = DAG.getTargetConstant(VssegInts[NF - 2], DL, XLenVT); in LowerINTRINSIC_VOID()
9630 SmallVector<SDValue, 12> Ops = {FixedIntrinsic->getChain(), IntID}; in LowerINTRINSIC_VOID()
5137 SDValue IntID = lowerVECTOR_SHUFFLE() local
9452 SDValue IntID = DAG.getTargetConstant( LowerINTRINSIC_W_CHAIN() local
9503 SDValue IntID = DAG.getTargetConstant(VlsegInts[NF - 2], DL, XLenVT); LowerINTRINSIC_W_CHAIN() local
9585 SDValue IntID = DAG.getTargetConstant( LowerINTRINSIC_VOID() local
9624 SDValue IntID = DAG.getTargetConstant(VssegInts[NF - 2], DL, XLenVT); LowerINTRINSIC_VOID() local
10786 SDValue IntID = DAG.getTargetConstant( lowerFixedLengthVectorLoadToRVV() local
10847 SDValue IntID = DAG.getTargetConstant( lowerFixedLengthVectorStoreToRVV() local
10894 unsigned IntID = lowerMaskedLoad() local
10972 unsigned IntID = lowerMaskedStore() local
11806 SDValue IntID = DAG.getTargetConstant(IsUnmasked ? Intrinsic::riscv_vlse lowerVPStridedLoad() local
11854 SDValue IntID = DAG.getTargetConstant(IsUnmasked ? Intrinsic::riscv_vsse lowerVPStridedStore() local
11946 unsigned IntID = lowerMaskedGather() local
12044 unsigned IntID = lowerMaskedScatter() local
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H A DRISCVISelDAGToDAG.cpp108 SDValue IntID = in PreprocessISelDAG() local
111 IntID, in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2378 Intrinsic::ID IntID = in computeKnownBitsForTargetNode() local
2380 switch (IntID) { in computeKnownBitsForTargetNode()
26327 Intrinsic::ID IntID = in ReplaceNodeResults() local
26329 switch (IntID) { in ReplaceNodeResults()
27975 SDValue IntID = HG->getIntID(); in LowerVECTOR_HISTOGRAM() local
27978 [[maybe_unused]] ConstantSDNode *CID = cast<ConstantSDNode>(IntID.getNode()); in LowerVECTOR_HISTOGRAM()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp20111 Intrinsic::ID IntID = in computeKnownBitsForTargetNode() local
20113 switch (IntID) { in computeKnownBitsForTargetNode()
/freebsd/sys/contrib/dev/acpica/
H A Dchanges.txt107 …IntID (GSIV) equal to the first argument of the call/invocation. The acpiexec code simulates the b…