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Searched refs:Insn (Results 1 – 25 of 61) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp46 uint64_t &Size, uint16_t &Insn) { in readInstruction16() argument
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
58 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
65 Insn = in readInstruction32()
91 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
95 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
99 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
103 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
107 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
111 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp92 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
95 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
98 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
101 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
105 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
108 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
111 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
115 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
119 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
122 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp51 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
54 Insn = in readInstruction32()
60 uint64_t &Size, uint64_t &Insn) { in readInstruction64() argument
62 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) | in readInstruction64()
70 uint64_t &Size, uint64_t &Insn) { in readInstruction48() argument
72 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | in readInstruction48()
79 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
81 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
156 static unsigned decodeCField(unsigned Insn) { in decodeCField() argument
157 return fieldFromInstruction(Insn, 6, 6); in decodeCField()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp278 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
281 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
285 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
287 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
290 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
293 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
296 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
299 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
304 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
307 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp55 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
59 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
63 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
67 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
74 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
81 uint32_t &Insn) { in readInstruction32() argument
89 Insn = in readInstruction32()
95 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
106 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
110 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1); in PostOperandDecodeAdjust()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp105 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn,
133 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn,
189 static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
231 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
237 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
241 static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
244 static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
247 static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
251 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
254 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp44 SmallVectorImpl<ImmInsnModel> &Insn) { in tryToreplicateChunks() argument
67 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in tryToreplicateChunks()
80 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
95 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
151 SmallVectorImpl<ImmInsnModel> &Insn) { in trySequenceOfOnes() argument
223 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in trySequenceOfOnes()
226 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx), in trySequenceOfOnes()
235 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx), in trySequenceOfOnes()
317 SmallVectorImpl<ImmInsnModel> &Insn) { in tryOrrOfLogicalImmediates() argument
330 Insn.push_back({AArch64::ORRXri, 0, Encoding1}); in tryOrrOfLogicalImmediates()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFPreserveStaticOffset.cpp208 GEPChainInfo &GEP, T *Insn) { in fillCommonArgs() argument
212 unsigned AlignShiftValue = Log2_64(Insn->getAlign().value()); in fillCommonArgs()
214 Args.push_back(ConstantInt::get(Int1Ty, Insn->isVolatile())); in fillCommonArgs()
215 Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getOrdering())); in fillCommonArgs()
216 Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getSyncScopeID())); in fillCommonArgs()
288 static void reconstructCommon(CallInst *Call, GetElementPtrInst *GEP, T *Insn, in reconstructCommon() argument
290 Insn->setVolatile(getOperandAsUnsigned(Call, 1 + Delta)); in reconstructCommon()
291 Insn->setOrdering((AtomicOrdering)getOperandAsUnsigned(Call, 2 + Delta)); in reconstructCommon()
292 Insn->setSyncScopeID(getOperandAsUnsigned(Call, 3 + Delta)); in reconstructCommon()
294 Insn->setAlignment(Align(1ULL << AlignShiftValue)); in reconstructCommon()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionPrecedenceTracking.cpp69 const Instruction *Insn) { in isPreceededBySpecialInstruction() argument
71 getFirstSpecialInstruction(Insn->getParent()); in isPreceededBySpecialInstruction()
72 return MaybeFirstSpecial && MaybeFirstSpecial->comesBefore(Insn); in isPreceededBySpecialInstruction()
82 for (const Instruction &Insn : *BB) in validate()
83 if (isSpecialInstruction(&Insn)) { in validate()
84 assert(It->second == &Insn && in validate()
131 const Instruction *Insn) const { in isSpecialInstruction()
137 return !isGuaranteedToTransferExecutionToSuccessor(Insn); in isSpecialInstruction()
141 const Instruction *Insn) const { in isSpecialInstruction()
143 if (match(Insn, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) in isSpecialInstruction()
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H A DGuardUtils.cpp40 for (auto &Insn : *DeoptBB) { in isGuardAsWidenableBranch()
41 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>())) in isGuardAsWidenableBranch()
43 if (Insn.mayHaveSideEffects()) in isGuardAsWidenableBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp182 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() argument
183 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI()
184 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeI()
188 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { in DecodeSrcAddrModeII() argument
189 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII()
190 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeII()
194 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() argument
195 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode()
196 unsigned Ad = fieldFromInstruction(Insn, 7, 1); in DecodeDstAddrMode()
234 uint64_t Insn = support::endian::read16le(Bytes.data()); in getInstructionI() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DInstructionPrecedenceTracking.h60 LLVM_ABI bool isPreceededBySpecialInstruction(const Instruction *Insn);
67 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
114 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { in isDominatedByICFIFromSameBlock() argument
115 return isPreceededBySpecialInstruction(Insn); in isDominatedByICFIFromSameBlock()
118 bool isSpecialInstruction(const Instruction *Insn) const override;
137 bool isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) { in isDominatedByMemoryWriteFromSameBlock() argument
138 return isPreceededBySpecialInstruction(Insn); in isDominatedByMemoryWriteFromSameBlock()
141 bool isSpecialInstruction(const Instruction *Insn) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp127 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, in decodeMemoryOpValue() argument
130 unsigned Register = (Insn >> 16) & 0xf; in decodeMemoryOpValue()
135 unsigned Offset = (Insn & 0xffff); in decodeMemoryOpValue()
143 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
161 Insn = Make_64(Hi, Lo); in readInstruction64()
171 uint64_t Insn, Hi; in getInstruction() local
174 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
177 uint8_t InstClass = getInstClass(Insn); in getInstruction()
178 uint8_t InstMode = getInstMode(Insn); in getInstruction()
180 getInstSize(Insn) != BPF_DW && in getInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldELFMips.cpp215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in applyMIPSRelocation() local
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff); in applyMIPSRelocation()
234 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff); in applyMIPSRelocation()
238 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff); in applyMIPSRelocation()
242 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
245 Insn = (Insn & 0xffe00000) | (Value & 0x001fffff); in applyMIPSRelocation()
246 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
250 Insn = (Insn & 0xfc000000) | (Value & 0x03ffffff); in applyMIPSRelocation()
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H A DRuntimeDyldMachOARM.h271 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
274 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) | in resolveRelocation()
278 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
279 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp539 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
543 static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
547 static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
552 decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
556 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
560 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
564 static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
576 static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
582 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, in decodeRVCInstrRdRs1ImmZero() argument
586 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1ImmZero()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/Disassembler/
H A DM68kDisassembler.cpp114 static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn, in DecodeCCRCRegisterClass() argument
120 static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, APInt &Insn, in DecodeSRCRegisterClass() argument
155 auto MakeUp = [&](APInt &Insn, unsigned InstrBits) { in getInstruction() argument
156 unsigned Idx = Insn.getBitWidth() >> 3; in getInstruction()
158 if (RoundUp > Insn.getBitWidth()) in getInstruction()
159 Insn = Insn.zext(RoundUp); in getInstruction()
162 Insn.insertBits(support::endian::read16be(&Bytes[Idx]), Idx * 8, 16); in getInstruction()
165 APInt Insn(16, support::endian::read16be(Bytes.data())); in getInstruction() local
170 Result = decodeInstruction(DecoderTable80, Instr, Insn, Address, this, STI, in getInstruction()
/freebsd/sbin/ipfw/tests/
H A Dtest_add_rule.py29 from atf_python.sys.netpfil.ipfw.insns import Insn
427 Insn(IpFwOpcode.O_EXTERNAL_DATA, arg1=123),
456 Insn(IpFwOpcode.O_COUNT),
486 Insn(IpFwOpcode.O_PROTO, arg1=6),
502 Insn(IpFwOpcode.O_PROTO, arg1=6),
523 Insn(IpFwOpcode.O_REJECT, arg1=IcmpRejectCode.ICMP_REJECT_ABORT),
530 Insn(
541 Insn(IpFwOpcode.O_REJECT, arg1=IcmpRejectCode.ICMP_UNREACH_HOST),
548 Insn(IpFwOpcode.O_REJECT, arg1=IcmpRejectCode.ICMP_REJECT_RST),
555 Insn(IpFwOpcode.O_UNREACH6, arg1=Icmp6RejectCode.ICMP6_UNREACH_RST),
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/freebsd/tests/atf_python/sys/netpfil/ipfw/
H A Dinsns.py188 class Insn(BaseInsn): class
209 class InsnUnknown(Insn):
227 class InsnEmpty(Insn):
239 class InsnComment(Insn):
278 class InsnProto(Insn):
291 class InsnU32(Insn):
530 class InsnReject(Insn):
566 class InsnPorts(Insn):
616 class InsnIp6(Insn):
663 AttrDescr(IpFwOpcode.O_UNREACH6, Insn),
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp152 CodeGenInstruction Insn(Operator); in evaluateExpansion() local
154 if (Insn.isCodeGenOnly || Insn.isPseudo) in evaluateExpansion()
159 if (Insn.Operands.size() != Dag->getNumArgs()) in evaluateExpansion()
180 for (const auto &Op : Insn.Operands) in evaluateExpansion()
189 for (const auto &[Idx, DstOp] : enumerate(Insn.Operands)) { in evaluateExpansion()
215 Expansions.emplace_back(SourceInsn, Insn, OperandMap); in evaluateExpansion()
H A DDecoderEmitter.cpp538 void insnWithID(insn_t &Insn, unsigned Opcode) const { in insnWithID() argument
541 Insn.resize(std::max(BitWidth, Bits.getNumBits()), BitValue::BIT_UNSET); in insnWithID()
551 Insn[i] = BitValue::BIT_UNSET; in insnWithID()
553 Insn[i] = BitValue(Bits, i); in insnWithID()
563 std::pair<bool, uint64_t> fieldFromInsn(const insn_t &Insn, unsigned StartBit,
587 unsigned getIslands(std::vector<Island> &Islands, const insn_t &Insn) const;
664 insn_t Insn; in Filter() local
667 Owner.insnWithID(Insn, OpcPair.EncodingID); in Filter()
670 auto [Ok, Field] = Owner.fieldFromInsn(Insn, StartBit, NumBits); in Filter()
1127 std::pair<bool, uint64_t> FilterChooser::fieldFromInsn(const insn_t &Insn, in fieldFromInsn() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1880 InternalInstruction Insn; in getInstruction() local
1881 memset(&Insn, 0, sizeof(InternalInstruction)); in getInstruction()
1882 Insn.bytes = Bytes; in getInstruction()
1883 Insn.startLocation = Address; in getInstruction()
1884 Insn.readerCursor = Address; in getInstruction()
1885 Insn.mode = fMode; in getInstruction()
1887 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) || in getInstruction()
1888 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 || in getInstruction()
1889 readOperands(&Insn)) { in getInstruction()
1890 Size = Insn.readerCursor - Address; in getInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp450 uint64_t &Size, uint64_t &Insn, in readInstruction16() argument
461 Insn = (Bytes[1] << 8) | Bytes[0]; in readInstruction16()
469 uint64_t &Size, uint64_t &Insn, in readInstruction24() argument
480 Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); in readInstruction24()
492 uint64_t Insn; in getInstruction() local
497 Result = readInstruction16(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
501 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); in getInstruction()
509 Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
513 Result = decodeInstruction(DecoderTable24, MI, Insn, Address, this, STI); in getInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp277 uint64_t &Size, uint32_t &Insn, in readInstruction32() argument
286 Insn = IsLittleEndian in readInstruction32()
299 uint32_t Insn; in getInstruction() local
302 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); in getInstruction()
310 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); in getInstruction()
314 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); in getInstruction()
320 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); in getInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp164 uint32_t Insn; in getInstruction() local
174 Insn = support::endian::read32le(Bytes.data()); in getInstruction()
176 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); in getInstruction()

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