Lines Matching refs:Insn
92 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
95 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
98 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
101 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
105 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
108 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
111 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
115 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
119 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
122 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
126 static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
129 static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address,
132 static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn,
136 static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
142 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFIOARr() argument
145 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIOARr()
146 addr |= fieldFromInstruction(Insn, 9, 2) << 4; in decodeFIOARr()
147 unsigned reg = fieldFromInstruction(Insn, 4, 5); in decodeFIOARr()
155 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFIORdA() argument
158 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIORdA()
159 addr |= fieldFromInstruction(Insn, 9, 2) << 4; in decodeFIORdA()
160 unsigned reg = fieldFromInstruction(Insn, 4, 5); in decodeFIORdA()
168 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFIOBIT() argument
170 unsigned addr = fieldFromInstruction(Insn, 3, 5); in decodeFIOBIT()
171 unsigned b = fieldFromInstruction(Insn, 0, 3); in decodeFIOBIT()
186 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFRd() argument
188 unsigned d = fieldFromInstruction(Insn, 4, 5); in decodeFRd()
195 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFLPMX() argument
197 if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail) in decodeFLPMX()
203 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, in decodeFFMULRdRr() argument
206 unsigned d = fieldFromInstruction(Insn, 4, 3) + 16; in decodeFFMULRdRr()
207 unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; in decodeFFMULRdRr()
217 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, in decodeFMOVWRdRr() argument
220 unsigned r = fieldFromInstruction(Insn, 4, 4) * 2; in decodeFMOVWRdRr()
221 unsigned d = fieldFromInstruction(Insn, 0, 4) * 2; in decodeFMOVWRdRr()
231 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFWRdK() argument
233 unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25 in decodeFWRdK()
235 k |= fieldFromInstruction(Insn, 0, 4); in decodeFWRdK()
236 k |= fieldFromInstruction(Insn, 6, 2) << 4; in decodeFWRdK()
247 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, in decodeFMUL2RdRr() argument
250 unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16; in decodeFMUL2RdRr()
251 unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16; in decodeFMUL2RdRr()
261 static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeMemri() argument
266 if (Insn > 127) in decodeMemri()
271 MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30)); in decodeMemri()
273 Inst.addOperand(MCOperand::createImm(Insn & 0x3f)); in decodeMemri()
278 static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address, in decodeFBRk() argument
281 switch (Insn & 0xf000) { in decodeFBRk()
292 int16_t Offset = ((int16_t)((Insn & 0xfff) << 4)) >> 3; in decodeFBRk()
297 static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn, in decodeCondBranch() argument
307 int16_t Offset = ((int16_t)((Insn & 0x3f8) << 6)) >> 8; in decodeCondBranch()
310 auto NotAlias = [&Insn](const std::pair<unsigned, unsigned> &I) { in decodeCondBranch()
311 return (Insn & 0x407) != I.first; in decodeCondBranch()
323 Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk); in decodeCondBranch()
324 Inst.addOperand(MCOperand::createImm(Insn & 7)); in decodeCondBranch()
331 static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn, in decodeLoadStore() argument
335 unsigned RegVal = GPRDecoderTable[(Insn >> 4) & 0x1f]; in decodeLoadStore()
338 if ((Insn & 0xf000) == 0x8000) { in decodeLoadStore()
339 unsigned RegBase = (Insn & 0x8) ? AVR::R29R28 : AVR::R31R30; in decodeLoadStore()
340 unsigned Offset = Insn & 7; // We need not consider offset > 7. in decodeLoadStore()
341 if ((Insn & 0x200) == 0) { // Decode LDD. in decodeLoadStore()
373 if ((Insn & 0xfc00) != 0x9000 || (Insn & 0xf) == 0) in decodeLoadStore()
378 switch (Insn & 0xc) { in decodeLoadStore()
393 switch (Insn & 0x203) { in decodeLoadStore()
421 if ((Insn & 0x200) == 0) { // This is a load instruction. in decodeLoadStore()
437 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
444 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
450 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
458 Insn = in readInstruction32()
480 uint32_t Insn; in getInstruction() local
486 Result = readInstruction16(Bytes, Address, Size, Insn); in getInstruction()
493 Result = decodeInstruction(DecoderTableAVRTiny16, Instr, Insn, Address, in getInstruction()
500 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address, in getInstruction()
507 Result = decodeLoadStore(Instr, Insn, Address, this); in getInstruction()
514 Result = readInstruction32(Bytes, Address, Size, Insn); in getInstruction()
519 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address, in getInstruction()