Home
last modified time | relevance | path

Searched refs:Indexed (Results 1 – 25 of 41) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/
H A DOperations.cpp283 Type *Indexed = ExtractValueInst::getIndexedType(Cur[0]->getType(), in validInsertValueIndex() local
285 return Indexed == Cur[1]->getType(); in validInsertValueIndex()
294 while (Type *Indexed = ExtractValueInst::getIndexedType(BaseTy, I)) { in validInsertValueIndex() local
295 if (Indexed == Cur[1]->getType()) in validInsertValueIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt19 - Vector Extract Unsigned Byte Left/Right-Indexed:
22 // Left-Indexed
27 // Right-Indexed
503 - Load/Store Vector Indexed: lxvx stxvx
527 - Load as Integer Byte/Halfword & Zero Indexed: lxsibzx lxsihzx
535 - Store as Integer Byte/Halfword Indexed: stxsibx stxsihx
543 - Load Vector Halfword*8/Byte*16 Indexed: lxvh8x lxvb16x
553 - Store Vector Halfword*8/Byte*16 Indexed: stxvh8x stxvb16x
571 - Load Vector Word & Splat Indexed: lxvwsx
H A DPPCScheduleP8.td
H A DPPCInstrP10.td2401 // Indexed vector insert element
2435 // Indexed vector insert element
2448 // Indexed vector insert element
H A DPPCInstrVSX.td1678 // Load as Integer Byte/Halfword & Zero Indexed
1684 // Load Vector Halfword*8/Byte*16 Indexed
1688 // Load Vector Indexed
1699 // Load Vector Word & Splat Indexed
1716 // Store as Integer Byte/Halfword Indexed
1726 // Store Vector Halfword*8/Byte*16 Indexed
1730 // Store Vector Indexed
/freebsd/contrib/llvm-project/llvm/include/llvm/CGData/
H A DCodeGenData.inc51 /* Indexed codegen data format version (start from 1). */
/freebsd/contrib/file/magic/Magdir/
H A Dgimp38 >22 belong 2 Indexed Color
H A Dmap298 # POIs,Indexed POIs,Polylines or Polygons or first map level
H A Dimages2090 # The color mode; 0~Bitmap 1~Grayscale 2~Indexed 3~RGB 4~CMYK 7~Multichannel 9~Duotone 9~Lab
4030 >7 ubyte 0x00 3D Coordinates with Indexed Color
4031 >7 ubyte 0x01 2D Coordinates with Indexed Color
4613 >>>12 uleshort 8 \b, Indexed
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp7432 enum class FMAInstKind { Default, Indexed, Accumulator }; enumerator
7495 else if (kind == FMAInstKind::Indexed) in genFusedMultiply()
7648 FMAInstKind::Indexed); in genFusedMultiplyIdx()
7664 FMAInstKind::Indexed, &NewVR); in genFusedMultiplyIdxNeg()
8251 FMAInstKind::Indexed); in genAlternativeCodeSequence()
8257 FMAInstKind::Indexed); in genAlternativeCodeSequence()
8264 FMAInstKind::Indexed); in genAlternativeCodeSequence()
8270 FMAInstKind::Indexed); in genAlternativeCodeSequence()
8277 FMAInstKind::Indexed); in genAlternativeCodeSequence()
8289 FMAInstKind::Indexed); in genAlternativeCodeSequence()
[all …]
H A DSVEInstrFormats.td2539 // SVE Floating Point Multiply-Add - Indexed Group
2609 // SVE Floating Point Multiply - Indexed Group
2718 // SVE Floating Point Complex Multiply-Add - Indexed Group
2916 // SVE2 Floating Point Widening Multiply-Add - Indexed Group
3653 // SVE2 Integer Multiply-Add - Indexed Group
3704 // SVE2 Integer Multiply-Add Long - Indexed Group
3764 // SVE Integer Dot Product Group - Indexed Group
3864 // SVE2 Complex Integer Dot Product - Indexed Group
3913 // SVE2 Complex Multiply-Add - Indexed Group
3981 // SVE2 Integer Multiply - Indexed Group
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXTHead.td373 // T-Head Load/Store Indexed instructions.
430 // T-Head Load/Store Indexed instructions.
447 // T-Head Load/Store Indexed instructions for floating point registers.
H A DRISCVFeatures.td1154 "T-Head FP Indexed Memory Operations">;
1157 "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">;
1168 "T-Head Indexed Memory Operations">;
1171 "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">;
H A DRISCVSchedSiFive7.td510 // scheduled accordingly. Indexed loads and stores operate at one element per
512 // so they cannot be scheduled. Indexed and strided loads and stores have LMUL
612 // Indexed segment loads and stores operate at the same rate as strided ones,
H A DRISCVInstrInfoV.td232 // Vector Indexed Loads and Stores
297 // Indexed Segment Loads and Stores
1771 // Vector Indexed Instructions
1820 // Vector Indexed Segment Instructions
H A DRISCVScheduleV.td304 // 7.6. Vector Indexed Instructions
560 // 7.6. Vector Indexed Instructions
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9504 bool Indexed = AM != ISD::UNINDEXED; in getLoad() local
9505 assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!"); in getLoad()
9507 SDVTList VTs = Indexed ? in getLoad()
9632 bool Indexed = AM != ISD::UNINDEXED; in getStore() local
9633 assert((Indexed || Offset.isUndef()) && "Unindexed store with an offset!"); in getStore()
9634 SDVTList VTs = Indexed ? getVTList(Ptr.getValueType(), MVT::Other) in getStore()
9726 bool Indexed = AM != ISD::UNINDEXED; in getLoadVP() local
9727 assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!"); in getLoadVP()
9729 SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other) in getLoadVP()
9821 bool Indexed = AM != ISD::UNINDEXED; in getStoreVP() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td648 // lxaaddr : like bdxaddr, but used for Load (Logical) Indexed Address
/freebsd/crypto/openssl/doc/internal/man7/
H A Dbuild.info.pod432 =head2 Indexed statements
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td712 // Indexed Jump or Execute.
H A DARCInstrInfo.td602 // Indexed Jump or Execute.
/freebsd/contrib/llvm-project/llvm/include/llvm/ProfileData/
H A DInstrProfData.inc724 /* Indexed profile format version (start from 1). */
/freebsd/contrib/llvm-project/compiler-rt/include/profile/
H A DInstrProfData.inc724 /* Indexed profile format version (start from 1). */
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td623 // Indexed loads and stores.
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td655 // Indexed, indirect register and indirect autoincrement modes

12