| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 190 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
764 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchRsrcRegSetup()
798 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
813 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
824 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
828 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
833 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
837 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
864 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
868 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
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| H A D | SIRegisterInfo.cpp | 214 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
231 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
1583 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1626 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1679 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1810 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1909 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1942 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
2023 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
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| H A D | SILowerControlFlow.cpp | 237 .addReg(Exec, RegState::ImplicitDefine); in emitIf()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 229 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
664 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
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| H A D | SystemZShortenInst.cpp | 148 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
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| H A D | SystemZFrameLowering.cpp | 423 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
1196 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| H A D | SystemZInstrInfo.cpp | 241 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
923 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 545 Inst.addReg(Reg, RegState::ImplicitDefine); in lowerInlineAsm()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 65 ImplicitDefine = Implicit | Define, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 1126 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
1419 MIB.addReg(Reg, RegState::ImplicitDefine); in EmitSpecialNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2188 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2211 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2270 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2273 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2824 .addReg(CRReg, RegState::ImplicitDefine); in optimizeCmpPostRA()
3326 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 573 .addReg(Reg, RegState::ImplicitDefine) in ExpandMOVEM()
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| H A D | M68kFrameLowering.cpp | 886 I.addReg(Info.getReg(), RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1111 .addDef(Hexagon::R29, RegState::ImplicitDefine) in expandPostRAPseudo()
1112 .addDef(Hexagon::R30, RegState::ImplicitDefine) in expandPostRAPseudo()
1113 .addDef(Hexagon::R14, RegState::ImplicitDefine) in expandPostRAPseudo()
1114 .addDef(Hexagon::R15, RegState::ImplicitDefine) in expandPostRAPseudo()
1115 .addDef(Hexagon::R28, RegState::ImplicitDefine); in expandPostRAPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 247 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| H A D | ARMExpandPseudoInsts.cpp | 659 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
827 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
2799 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| H A D | ARMFrameLowering.cpp | 1932 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
1949 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
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| H A D | ARMBaseInstrInfo.cpp | 1449 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1495 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1525 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1550 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| H A D | ARMLoadStoreOptimizer.cpp | 961 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 2133 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2134 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
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| H A D | MipsSEInstrInfo.cpp | 134 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
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| H A D | MipsSEISelDAGToDAG.cpp | 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 1613 PopBuilder.addDef(FixedCSRFIMap[i].first, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6109 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6138 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6220 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
7054 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7076 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7085 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1637 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
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