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Searched refs:ImplicitDefine (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp190 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
811 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchRsrcRegSetup()
845 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
860 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
871 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
875 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
880 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
884 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
911 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
915 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
H A DSIRegisterInfo.cpp220 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
238 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
1828 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1871 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1926 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
2087 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
2186 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
2219 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
2303 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
H A DSILowerControlFlow.cpp246 .addReg(Exec, RegState::ImplicitDefine); in emitIf()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp226 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
670 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
H A DSystemZShortenInst.cpp145 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
H A DSystemZFrameLowering.cpp425 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
1228 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
H A DSystemZInstrInfo.cpp243 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
947 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp545 Inst.addReg(Reg, RegState::ImplicitDefine); in lowerInlineAsm()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h66 ImplicitDefine = Implicit | Define, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp1128 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
1420 MIB.addReg(Reg, RegState::ImplicitDefine); in EmitSpecialNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1776 .addReg(PPC::CARRY, RegState::ImplicitDefine); in copyPhysReg()
2211 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2234 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2293 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2296 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2847 .addReg(CRReg, RegState::ImplicitDefine); in optimizeCmpPostRA()
3357 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kFrameLowering.cpp886 I.addReg(Info.getReg(), RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
H A DM68kInstrInfo.cpp616 .addReg(Reg, RegState::ImplicitDefine) in ExpandMOVEM()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1114 .addDef(Hexagon::R29, RegState::ImplicitDefine) in expandPostRAPseudo()
1115 .addDef(Hexagon::R30, RegState::ImplicitDefine) in expandPostRAPseudo()
1116 .addDef(Hexagon::R14, RegState::ImplicitDefine) in expandPostRAPseudo()
1117 .addDef(Hexagon::R15, RegState::ImplicitDefine) in expandPostRAPseudo()
1118 .addDef(Hexagon::R28, RegState::ImplicitDefine); in expandPostRAPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp246 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMExpandPseudoInsts.cpp658 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
826 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
2841 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
H A DARMBaseInstrInfo.cpp1290 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1336 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1366 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1391 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMFrameLowering.cpp2158 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
2175 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
H A DARMLoadStoreOptimizer.cpp958 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2148 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2149 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
H A DMipsSEInstrInfo.cpp132 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp52 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6166 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6195 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6277 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
7129 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7151 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7160 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7177 BuildMI.addReg(SuperReg, RegState::ImplicitDefine); in breakPartialRegDependency()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp3590 .addReg(AArch64::X0, RegState::ImplicitDefine) in spillCalleeSavedRegisters()
4671 .addReg(AArch64::NZCV, RegState::ImplicitDefine) in expandFillPPRFromZPRSlotPseudo()
4677 .addReg(AArch64::NZCV, RegState::ImplicitDefine) in expandFillPPRFromZPRSlotPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp2225 PopBuilder.addDef(FixedCSRFIMap[i], RegState::ImplicitDefine); in restoreCalleeSavedRegisters()

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