Searched refs:Imm12 (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 400 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
402 assert(Imm12 < (1 << 12) && "Imm too large!");
404 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
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| H A D | ARMMCCodeEmitter.cpp | 970 unsigned Reg = 0, Imm12 = 0; in getMVEShiftImmOpValue()
977 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
1007 Imm12 = Offset; in getAddrModeImm12OpValue()
1009 uint32_t Binary = Imm12 & 0xfff; in getAddrModeImm12OpValue()
981 unsigned Reg = 0, Imm12 = 0; getAddrModeImm12OpValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 267 int64_t Imm12 = -(0x800 - (Val & 0xfff)); in generateInstSeq() local
268 int64_t AdjustedVal = Val - Imm12; in generateInstSeq()
274 TmpSeq.emplace_back(RISCV::ADDI, Imm12); in generateInstSeq()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaOperands.td | 41 def Imm12_AsmOperand : ImmAsmOperand<"Imm12">;
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | ELF_riscv.cpp | 216 uint32_t Imm12 = extractBits(Value, 12, 1) << 31; in applyFixup() local
222 (RawInstr & 0x1FFF07F) | Imm12 | Imm10_5 | Imm4_1 | Imm11; in applyFixup()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 7007 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | in DecodeT2AddSubSPImm() local
7025 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 in DecodeT2AddSubSPImm()
7028 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 in DecodeT2AddSubSPImm()
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