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Searched refs:Imm (Results 1 – 25 of 400) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immediate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
99 return ShOp | (Imm << 3); in getSORegOpc()
106 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } in getSOImmValImm() argument
109 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } in getSOImmValRot() argument
115 inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
118 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
121 unsigned TZ = llvm::countr_zero(Imm); in getSOImmValRotate()
128 if ((llvm::rotr<uint32_t>(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
133 if (Imm & 63U) { in getSOImmValRotate()
134 unsigned TZ2 = llvm::countr_zero(Imm & ~63U); in getSOImmValRotate()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp236 static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, in decodeCallOperand() argument
238 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeCallOperand()
240 MCOperand::createImm(SignExtend64<20>(Imm << 2) + (Address & 0x3))); in decodeCallOperand()
244 static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, in decodeJumpOperand() argument
246 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeJumpOperand()
247 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
251 static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, in decodeBranchOperand() argument
258 assert(isUInt<12>(Imm) && "Invalid immediate"); in decodeBranchOperand()
259 if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true, in decodeBranchOperand()
261 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeBranchOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp61 int64_t Imm = Op.getImm(); in printU16ImmOperand() local
62 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
63 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
84 uint64_t Imm = MI->getOperand(OpNo).getImm(); in printFP64ImmOperand() local
85 if (STI.hasFeature(AMDGPU::Feature64BitLiterals) && Lo_32(Imm)) in printFP64ImmOperand()
86 O << "lit64(" << formatHex(static_cast<uint64_t>(Imm)) << ')'; in printFP64ImmOperand()
88 O << formatHex(static_cast<uint64_t>(Hi_32(Imm))); in printFP64ImmOperand()
101 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
102 if (Imm != 0) { in printOffset()
109 O << formatDec(SignExtend32<24>(Imm)); in printOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp183 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
184 if (!isUInt<N>(Imm)) in decodeUImmOperand()
186 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
191 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
192 if (!isUInt<N>(Imm)) in decodeSImmOperand()
194 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
198 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
201 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
204 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU2ImmOperand() argument
207 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
46 unsigned Shamt = llvm::countr_zero(Imm); in GetInstSeqLsSLL()
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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H A DMipsISelDAGToDAG.h93 virtual bool selectVSplat(SDNode *N, APInt &Imm,
95 virtual bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
99 bool selectVSplatUimm(SDValue N, SDValue &Imm) const { in selectVSplatUimm() argument
100 return selectVSplatCommon(N, Imm, false, Bits); in selectVSplatUimm()
104 bool selectVSplatSimm(SDValue N, SDValue &Imm) const { in selectVSplatSimm() argument
105 return selectVSplatCommon(N, Imm, true, Bits); in selectVSplatSimm()
108 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
111 virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const;
114 virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
117 virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaOperands.td26 def imm8 : Immediate<i32, [{ return Imm >= -128 && Imm <= 127; }], "Imm8_AsmOperand"> {
34 def imm8_sh8 : Immediate<i32, [{ return Imm >= -32768 && Imm <= 32512 && ((Imm & 0xFF) == 0); }],
42 def imm8n_7: Immediate<i32, [{ return Imm >= -8 && Imm <= 7; }], "Imm8n_7_AsmOperand"> {
49 def imm64n_4n: Immediate<i32, [{ return Imm >= -64 && Imm <= -4; }], "Imm64n_4n_AsmOperand"> {
56 def imm12 : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12_AsmOperand"> {
63 def imm12m : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12m_AsmOperand"> {
70 def uimm4 : Immediate<i32, [{ return Imm >= 0 && Imm <= 15; }], "Uimm4_AsmOperand"> {
77 def uimm5 : Immediate<i32, [{ return Imm >= 0 && Imm <= 31; }], "Uimm5_AsmOperand"> {
84 def imm1_16 : Immediate<i32, [{ return Imm >= 1 && Imm <= 16; }], "Imm1_16_AsmOperand"> {
91 def imm1n_15: Immediate<i32, [{ return Imm >= -1 && Imm <= 15 && Imm != 0; }], "Imm1n_15_AsmOperand…
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp128 unsigned Imm = MI->getOperand(OpNo).getImm(); in printCSRSystemRegister() local
129 auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm); in printCSRSystemRegister()
138 markup(O, Markup::Register) << formatImm(Imm); in printCSRSystemRegister()
184 unsigned Imm = MI->getOperand(OpNo).getImm(); in printFPImmOperand() local
185 if (Imm == 1) { in printFPImmOperand()
187 } else if (Imm == 30) { in printFPImmOperand()
189 } else if (Imm == 31) { in printFPImmOperand()
192 float FPVal = RISCVLoadFPImm::getFPImm(Imm); in printFPImmOperand()
217 unsigned Imm = MI->getOperand(OpNo).getImm(); in printVTypeI() local
220 if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED || in printVTypeI()
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H A DRISCVBaseInfo.cpp209 APInt Imm = FPImm.bitcastToAPInt(); in getLoadFPImm() local
211 if (Imm.extractBitsAsZExtValue(21, 0) != 0) in getLoadFPImm()
214 bool Sign = Imm.extractBitsAsZExtValue(1, 31); in getLoadFPImm()
215 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21); in getLoadFPImm()
216 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23); in getLoadFPImm()
236 float RISCVLoadFPImm::getFPImm(unsigned Imm) { in getFPImm() argument
237 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate"); in getFPImm()
241 if (Imm == 0) { in getFPImm()
243 Imm = 16; in getFPImm()
246 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first; in getFPImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp22 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { in getChunk() argument
25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; in getChunk()
124 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { in updateImm() argument
129 Imm &= ~(Mask << (Idx * 16)); in updateImm()
132 Imm |= Mask << (Idx * 16); in updateImm()
134 return Imm; in updateImm()
373 static bool tryEorOfLogicalImmediates(uint64_t Imm, in tryEorOfLogicalImmediates() argument
383 if ((Imm & Mask) != ((Imm >> BigSize) & Mask)) { in tryEorOfLogicalImmediates()
394 uint64_t RunStarts = Imm & ~rotl<uint64_t>(Imm, 1); in tryEorOfLogicalImmediates()
436 uint64_t RotatedImm = rotr<uint64_t>(Imm, Rotation); in tryEorOfLogicalImmediates()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp101 int64_t Imm = MO.getImm(); in printCvtMode() local
105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
110 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
115 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG) in printCvtMode()
120 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
160 const int Imm = MO.getImm(); in printFTZFlag() local
161 if (Imm) in printFTZFlag()
168 int64_t Imm = MO.getImm(); in printCmpMode() local
171 switch (Imm) { in printCmpMode()
219 switch (Imm) { in printCmpMode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMIRFormatter.cpp20 std::optional<unsigned int> OpIdx, int64_t Imm) const { in printImm()
25 printSDelayAluImm(Imm, OS); in printImm()
28 MIRFormatter::printImm(OS, MI, OpIdx, Imm); in printImm()
37 StringRef Src, int64_t &Imm, in parseImmMnemonic() argument
43 return parseSDelayAluImmMnemonic(OpIdx, Imm, Src, ErrorCallback); in parseImmMnemonic()
50 void AMDGPUMIRFormatter::printSDelayAluImm(int64_t Imm, in printSDelayAluImm() argument
58 uint64_t Id0 = (Imm & 0xF); in printSDelayAluImm()
59 uint64_t Skip = ((Imm >> 4) & 0x7); in printSDelayAluImm()
60 uint64_t Id1 = ((Imm >> 7) & 0xF); in printSDelayAluImm()
94 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src, in parseSDelayAluImmMnemonic() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask,
53 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
56 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
59 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
62 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
66 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
70 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
74 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
81 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
105 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
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H A DX86ShuffleDecode.cpp26 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask, in DecodeINSERTPSMask() argument
35 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
36 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
37 unsigned CountS = SrcIsMem ? 0 : (Imm >> 6) & 3; in DecodeINSERTPSMask()
100 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, in DecodePSLLDQMask() argument
107 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask()
112 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, in DecodePSRLDQMask() argument
118 unsigned Base = i + Imm; in DecodePSRLDQMask()
125 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, in DecodePALIGNRMask() argument
131 unsigned Base = i + Imm; in DecodePALIGNRMask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp395 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, in decodeUImmOperand() argument
398 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
399 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
404 static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm, in decodeUImmOperandGE() argument
407 assert(isUInt<Width>(Imm) && "Invalid immediate"); in decodeUImmOperandGE()
409 if (Imm < LowerBound) in decodeUImmOperandGE()
412 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperandGE()
417 static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, in decodeUImmPlus1OperandGE() argument
420 assert(isUInt<Width>(Imm) && "Invalid immediate"); in decodeUImmPlus1OperandGE()
422 if ((Imm + 1) < LowerBound) in decodeUImmPlus1OperandGE()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp227 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
230 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
231 Inst.addOperand(MCOperand::createImm(Imm << S)); in decodeUImmOperand()
236 static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm, in decodeOImmOperand() argument
239 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeOImmOperand()
240 Inst.addOperand(MCOperand::createImm(Imm + 1)); in decodeOImmOperand()
244 static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address, in decodeLRW16Imm8() argument
246 assert(isUInt<8>(Imm) && "Invalid immediate"); in decodeLRW16Imm8()
247 if ((Imm >> 7) & 0x1) { in decodeLRW16Imm8()
248 Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2)); in decodeLRW16Imm8()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp67 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, in decodeCondBrTarget() argument
70 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
74 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, in decodeDirectBrTarget() argument
77 int32_t Offset = SignExtend32<24>(Imm); in decodeDirectBrTarget()
250 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
253 if (!isUInt<N>(Imm)) in decodeUImmOperand()
255 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
260 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, in decodeSImmOperand() argument
263 if (!isUInt<N>(Imm)) in decodeSImmOperand()
265 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp405 ImmOp Imm; member
428 Imm = o.Imm; in RISCVOperand()
526 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm) { in evaluateConstantImm()
528 Imm = CE->getValue(); in evaluateConstantImm()
541 int64_t Imm; in isBareSimmNLsb0() local
542 if (evaluateConstantImm(getImm(), Imm)) in isBareSimmNLsb0()
543 return isShiftedInt<N - 1, 1>(fixImmediateForRV32(Imm, isRV64Imm())); in isBareSimmNLsb0()
556 int64_t Imm; in isBareSimmN() local
557 if (evaluateConstantImm(getImm(), Imm)) in isBareSimmN()
558 return isInt<N>(fixImmediateForRV32(Imm, isRV64Imm())); in isBareSimmN()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp59 auto Imm = OffsetOp.getImm(); in printMemOperand() local
60 if (Imm >= 0) in printMemOperand()
61 O << " + " << formatImm(Imm); in printMemOperand()
63 O << " - " << formatImm(-Imm); in printMemOperand()
85 int32_t Imm = Op.getImm(); in printBrTargetOperand() local
86 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); in printBrTargetOperand()
88 int16_t Imm = Op.getImm(); in printBrTargetOperand() local
89 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); in printBrTargetOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp49 static int64_t getInlineImmValF16(unsigned Imm);
50 static int64_t getInlineImmValBF16(unsigned Imm);
51 static int64_t getInlineImmVal32(unsigned Imm);
52 static int64_t getInlineImmVal64(unsigned Imm);
94 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, in decodeSOPPBrTarget() argument
100 int64_t Offset = SignExtend64<16>(Imm) * 4 + 4 + Addr; in decodeSOPPBrTarget()
104 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSOPPBrTarget()
107 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, in decodeSMEMOffset() argument
112 Offset = SignExtend64<24>(Imm); in decodeSMEMOffset()
114 Offset = Imm & 0xFFFFF; in decodeSMEMOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h53 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, in getIntImmCost() argument
66 if (Imm == 0) in getIntImmCost()
68 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
70 if (isInt<21>(Imm.getZExtValue())) in getIntImmCost()
72 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
73 if ((Imm.getSExtValue() & 0xFFFF) == 0) in getIntImmCost()
82 getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty,
85 return getIntImmCost(Imm, Ty, CostKind);
89 getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, in getIntImmCostIntrin() argument
91 return getIntImmCost(Imm, Ty, CostKind); in getIntImmCostIntrin()
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_hexagon.cpp43 encodeExtendedTransferImmediate(uint32_t Imm, RegNum DestReg, in encodeExtendedTransferImmediate() argument
49 Imm = Imm & 0x03f; in encodeExtendedTransferImmediate()
52 return PO_TFR_IMM | ParseBits | (Imm << 5) | (DestReg & REG_MASK); in encodeExtendedTransferImmediate()
56 encodeConstantExtender(uint32_t Imm) XRAY_NEVER_INSTRUMENT { in encodeConstantExtender() argument
68 Imm = Imm >> 6; in encodeConstantExtender()
70 const uint32_t high = (Imm & IMM_MASK_HIGH) << 16; in encodeConstantExtender()
71 const uint32_t low = Imm & IMM_MASK_LOW; in encodeConstantExtender()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp70 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
73 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
76 static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
79 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
82 static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm,
85 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
88 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
91 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
151 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
154 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp64 uint64_t Imm) const;
277 static uint32_t findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) { in findContiguousZerosAtLeast() argument
278 uint32_t HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm)); in findContiguousZerosAtLeast()
279 uint32_t LoLZ = llvm::countl_zero<uint32_t>(Lo_32(Imm)); in findContiguousZerosAtLeast()
291 uint64_t Imm) const { in selectI64ImmDirect()
292 unsigned TZ = llvm::countr_zero<uint64_t>(Imm); in selectI64ImmDirect()
293 unsigned LZ = llvm::countl_zero<uint64_t>(Imm); in selectI64ImmDirect()
294 unsigned TO = llvm::countr_one<uint64_t>(Imm); in selectI64ImmDirect()
295 unsigned LO = llvm::countl_one<uint64_t>(Imm); in selectI64ImmDirect()
296 uint32_t Hi32 = Hi_32(Imm); in selectI64ImmDirect()
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