104 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,  in decodeSOPPBrTarget()  argument
111   APInt SignedOffset(18, Imm * 4, true);  in decodeSOPPBrTarget()
116   return addOperand(Inst, MCOperand::createImm(Imm));  in decodeSOPPBrTarget()
119 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,  in decodeSMEMOffset()  argument
124     Offset = SignExtend64<24>(Imm);  in decodeSMEMOffset()
126     Offset = Imm & 0xFFFFF;  in decodeSMEMOffset()
128     Offset = SignExtend64<21>(Imm);  in decodeSMEMOffset()
153   static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm,            \
157     return addOperand(Inst, DAsm->DecoderName(Imm));                           \
164       MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,                           \
166     assert(Imm < (1 << 8) && "8-bit encoding");                                \
169         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
174   static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \
176     assert(Imm < (1 << EncSize) && #EncSize "-bit encoding");                  \
185                                 unsigned Imm, unsigned EncImm,  in decodeSrcOp()  argument
189   assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!");  in decodeSrcOp()
198   DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
205 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,  in decodeAV10()  argument
207   return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,  in decodeAV10()
213 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,  in decodeSrcReg9()  argument
216   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0,  in decodeSrcReg9()
224 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,  in decodeSrcA9()  argument
226   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0,  in decodeSrcA9()
233 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,  in decodeSrcAV10()  argument
236   return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0,  in decodeSrcAV10()
247 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,  in decodeSrcRegOrImm9()  argument
250   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,  in decodeSrcRegOrImm9()
258 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm,  in decodeSrcRegOrImmA9()  argument
261   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,  in decodeSrcRegOrImmA9()
267 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm,  in decodeSrcRegOrImmDeferred9()  argument
270   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,  in decodeSrcRegOrImmDeferred9()
308 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,  in DECODE_OPERAND_REG_8()
311   assert(isUInt<10>(Imm) && "10-bit encoding expected");  in DECODE_OPERAND_REG_8()
312   assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");  in DECODE_OPERAND_REG_8()
314   bool IsHi = Imm & (1 << 9);  in DECODE_OPERAND_REG_8()
315   unsigned RegIdx = Imm & 0xff;  in DECODE_OPERAND_REG_8()
321 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,  in DecodeVGPR_16_Lo128RegisterClass()  argument
323   assert(isUInt<8>(Imm) && "8-bit encoding expected");  in DecodeVGPR_16_Lo128RegisterClass()
325   bool IsHi = Imm & (1 << 7);  in DecodeVGPR_16_Lo128RegisterClass()
326   unsigned RegIdx = Imm & 0x7f;  in DecodeVGPR_16_Lo128RegisterClass()
331 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,  in decodeOperand_VSrcT16_Lo128()  argument
334   assert(isUInt<9>(Imm) && "9-bit encoding expected");  in decodeOperand_VSrcT16_Lo128()
337   bool IsVGPR = Imm & (1 << 8);  in decodeOperand_VSrcT16_Lo128()
339     bool IsHi = Imm & (1 << 7);  in decodeOperand_VSrcT16_Lo128()
340     unsigned RegIdx = Imm & 0x7f;  in decodeOperand_VSrcT16_Lo128()
344                                                    Imm & 0xFF, false, 16));  in decodeOperand_VSrcT16_Lo128()
347 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,  in decodeOperand_VSrcT16()  argument
350   assert(isUInt<10>(Imm) && "10-bit encoding expected");  in decodeOperand_VSrcT16()
353   bool IsVGPR = Imm & (1 << 8);  in decodeOperand_VSrcT16()
355     bool IsHi = Imm & (1 << 9);  in decodeOperand_VSrcT16()
356     unsigned RegIdx = Imm & 0xff;  in decodeOperand_VSrcT16()
360                                                    Imm & 0xFF, false, 16));  in decodeOperand_VSrcT16()
363 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,  in decodeOperand_KImmFP()  argument
367   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));  in decodeOperand_KImmFP()
390 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,  in decodeAVLdSt()  argument
395     Imm &= 511;  in decodeAVLdSt()
411         Imm |= 512;  in decodeAVLdSt()
418         Imm |= 512;  in decodeAVLdSt()
421   return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));  in decodeAVLdSt()
425 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,  in decodeAVLdSt()  argument
428   return decodeAVLdSt(Inst, Imm, Opw, Decoder);  in decodeAVLdSt()
431 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,  in decodeOperand_VSrc_f64()  argument
434   assert(Imm < (1 << 9) && "9-bit encoding");  in decodeOperand_VSrc_f64()
437                     DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,  in decodeOperand_VSrc_f64()
448 static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm,  in DECODE_SDWA()
452   return addOperand(Inst, DAsm->decodeVersionImm(Imm));  in DECODE_SDWA()
1277 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {  in decodeIntImmed()  argument
1280   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);  in decodeIntImmed()
1281   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?  in decodeIntImmed()
1282     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :  in decodeIntImmed()
1283     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));  in decodeIntImmed()
1287 static int64_t getInlineImmVal32(unsigned Imm) {  in getInlineImmVal32()  argument
1288   switch (Imm) {  in getInlineImmVal32()
1312 static int64_t getInlineImmVal64(unsigned Imm) {  in getInlineImmVal64()  argument
1313   switch (Imm) {  in getInlineImmVal64()
1337 static int64_t getInlineImmValF16(unsigned Imm) {  in getInlineImmValF16()  argument
1338   switch (Imm) {  in getInlineImmValF16()
1362 static int64_t getInlineImmValBF16(unsigned Imm) {  in getInlineImmValBF16()  argument
1363   switch (Imm) {  in getInlineImmValBF16()
1387 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) {  in getInlineImmVal16()  argument
1388   return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm)  in getInlineImmVal16()
1389                                                   : getInlineImmValF16(Imm);  in getInlineImmVal16()
1392 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm,  in decodeFPImmed()  argument
1394   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN &&  in decodeFPImmed()
1395          Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);  in decodeFPImmed()
1404     return MCOperand::createImm(getInlineImmVal32(Imm));  in decodeFPImmed()
1406     return MCOperand::createImm(getInlineImmVal64(Imm));  in decodeFPImmed()
1408     return MCOperand::createImm(getInlineImmVal16(Imm, Sema));  in decodeFPImmed()
1758 MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const {  in decodeVersionImm()
1765   auto [Version, W64, W32, MDP] = Encoding::decode(Imm);  in decodeVersionImm()
1768   if (Encoding::encode(Version, W64, W32, MDP) != Imm)  in decodeVersionImm()
1769     return MCOperand::createImm(Imm);  in decodeVersionImm()