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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,versatile-fpga-irq.txt3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
5 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
12 as the FPGA IRQ controller has no configuration options for interrupt
36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
37 output is simply connected to the input of another IRQ controller,
38 then the parent IRQ shall be specified in this property.
H A Dcdns,xtensa-pic.txt8 When it's 1, the first cell is the internal IRQ number.
9 When it's 2, the first cell is the IRQ number, and the second cell
11 Periferals are usually connected to a fixed external IRQ, but for different
12 core variants it may be mapped to different internal IRQ.
13 IRQ sensitivity and priority are fixed for each core variant and may not be
H A Dti,keystone-irq.txt1 Keystone 2 IRQ controller IP
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
H A Dsnps,archs-idu-intc.txt4 for dynamic IRQ routing, load balancing of common/external IRQs towards core
13 Value of the first cell specifies the "common" IRQ from peripheral to IDU.
45 interrupts = <0>; /* upstream idu IRQ #24 */
H A Dti,sci-intr.txt13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
16 +-------+ | . . |----->| IRQ |
52 - ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
57 For more details on TISCI IRQ resource management refer:
H A Dmarvell,sei.txt18 - interrupts: identifies the parent IRQ that will be triggered.
20 coming from the AP, should be 1. The cell is the IRQ
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Disil,isl12057.txt10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
26 the availability of an IRQ line connected to the SoC.
29 Example isl12057 node without IRQ#2 pin connected (no alarm support):
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
40 SoC, and the main function of the MPP used as IRQ line, i.e.
67 Example isl12057 node without IRQ#2 pin connected to the SoC but to a
H A Dxlnx-rtc.txt4 Separate IRQ lines for seconds and alarm
10 - interrupts: IRQ lines for the RTC.
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dfsl-imx-scc.txt6 - interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
8 SCM IRQ and SMN IRQ.
H A Dfsl-dcp.txt6 - interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
7 must be supplied, optionally Secure IRQ can be present, but
H A Datmel-crypto.txt10 - interrupts: Should contain the IRQ line for the AES.
30 - interrupts: Should contain the IRQ line for the TDES.
53 - interrupts: Should contain the IRQ line for the SHA.
/freebsd/sys/dts/
H A Dbindings-gpio.txt94 GPIO_PIN_IRQ_POL_EDG 0x0800 IRQ active single edge
95 GPIO_PIN_IRQ_POL_DBL 0x1000 IRQ active double edge
96 GPIO_PIN_IRQ_POL_LVL 0x2000 IRQ active level
97 GPIO_PIN_IRQ_DEBOUNCE 0x4000 Debounce on IRQ pin
102 &GPIO 2 0x00000801 /* GPIO[2]: IN, IRQ (edge) */
103 &GPIO 3 0x00004001 /* GPIO[3]: IN, IRQ (level) */
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-dsp-keystone.txt4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
H A D8xxx_gpio.txt28 - interrupts: Interrupt mapping for GPIO IRQ.
33 module as an IRQ controller.
65 Example of a peripheral using the GPIO module as an IRQ controller:
/freebsd/sys/contrib/device-tree/Bindings/iio/accel/
H A Dlis302.txt36 - st,irq{1,2}-disable: disable IRQ 1/2
37 - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition
38 - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition
39 - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition
40 - st,irq{1,2}-click: raise IRQ 1/2 on click condition
41 - st,irq-open-drain: consider IRQ lines open-drain
42 - st,irq-active-low: make IRQ lines active low
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dbrcm,bus-axi.txt11 Automatic detection of the IRQ number is not working on
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
14 IRQ used by the devices on the bus. The first address is just an index,
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax8925.txt6 - interrupts : IRQ line for the max8925 chip
10 - The cell is the max8925 local IRQ number
13 - maxim,tsc-irq: there are 2 IRQ lines for max8925, one is indicated in
H A Dda9055.txt25 - interrupts: IRQ line info for da9055 chip.
26 - interrupt-controller: da9055 has internal IRQs (has own IRQ domain).
27 - #interrupt-cells: Should be 1, is the local IRQ number for da9055.
H A Dhisilicon,hi655x.txt17 - interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
18 - pmic-gpios: The GPIO used by PMIC IRQ.
H A Dda9150.txt16 - interrupts: IRQ line info for da9150 chip.
17 - interrupt-controller: da9150 has internal IRQs (own IRQ domain).
/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-sdram-edac.txt7 - interrupts : Should contain the SDRAM ECC IRQ in the
8 appropriate format for the IRQ controller.
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-wmt.txt7 - interrupts : <IRQ> where IRQ is the interrupt number
H A Di2c-altera.txt8 - interrupts : <IRQ> where IRQ is the interrupt number.
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dhisilicon,hi6220-mailbox.txt24 dst_irq: IRQ identifier index number which used by MCU
25 ack_irq: IRQ identifier index number with generating a
36 flag" mode or IRQ generated mode to acknowledge a TX
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1023rdb.dts186 /* IRQ[0:3] are pulled up on board, set to active-low */
211 * IRQ[4:6] only for PCIe, set to active-high,
212 * IRQ[7] is pulled up on board, set to active-low
238 * IRQ[8:10] are pulled up on board, set to active-low
239 * IRQ[11] only for PCIe, set to active-high,

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