Searched refs:IMX7D_PLL_ENET_MAIN_100M_CLK (Results 1 – 10 of 10) sorted by relevance
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
142 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,148 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
111 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;142 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
235 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;262 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
131 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
156 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
52 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro