| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenHwModes.h | 30 struct HwMode { struct
31 HwMode(const Record *R);
51 const HwMode &getMode(unsigned Id) const { in getMode() argument
70 std::vector<HwMode> Modes;
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| H A D | CodeGenHwModes.cpp | 21 HwMode::HwMode(const Record *R) { in HwMode() function in HwMode
39 void HwMode::dump() const { dbgs() << Name << ": " << Features << '\n'; } in dump()
94 for (const HwMode &M : Modes) { in dump()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeEmitterGen.cpp | 73 const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
400 const CodeGenTarget &Target, unsigned HwMode) { in emitInstructionBaseValues() argument
402 if (HwMode == DefaultMode) in emitInstructionBaseValues()
406 << HWM.getModeName(HwMode, /*IncludeDefault=*/true) << "[] = {\n"; in emitInstructionBaseValues()
423 if (EBM.hasMode(HwMode)) { in emitInstructionBaseValues()
424 EncodingDef = EBM.get(HwMode); in emitInstructionBaseValues()
528 for (unsigned HwMode : HwModes) { in run() local
529 if (HwMode == DefaultMode) in run()
531 emitInstructionBaseValues(O, NumberedInstructions, Target, HwMode); in run()
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| H A D | RegisterBankEmitter.cpp | 99 const CodeGenRegisterClass *getRCWithLargestRegSize(unsigned HwMode) const { in getRCWithLargestRegSize()
100 return RCsWithLargestRegSize[HwMode]; in getRCWithLargestRegSize()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 398 unsigned HwMode; variable
427 const unsigned *Sizes, unsigned HwMode);
591 return Sizes[RegBankID + HwMode * NumRegBanks]; in getMaximumSize()
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| H A D | TargetRegisterInfo.h | 266 unsigned HwMode; variable
848 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVRegisterBankInfo.h | 34 RISCVRegisterBankInfo(unsigned HwMode);
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| H A D | RISCVRegisterBankInfo.cpp | 112 RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode) in RISCVRegisterBankInfo() argument
113 : RISCVGenRegisterBankInfo(HwMode) {} in RISCVRegisterBankInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.h | 26 LoongArchRegisterInfo(unsigned HwMode);
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| H A D | LoongArchRegisterInfo.cpp | 33 LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode) in LoongArchRegisterInfo() argument
36 /*PC*/ 0, HwMode) {} in LoongArchRegisterInfo()
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| H A D | LoongArch.td | 42 def LA64 : HwMode<"+64bit", [IsLA64]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 31 HexagonRegisterInfo(unsigned HwMode);
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| H A D | HexagonRegisterInfo.cpp | 51 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() argument
53 0/*PC*/, HwMode) {} in HexagonRegisterInfo()
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| H A D | Hexagon.td | 179 def Hvx64: HwMode<"+hvx-length64b", [UseHVX64B]>;
180 def Hvx128: HwMode<"+hvx-length128b", [UseHVX128B]>;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 61 HwMode(Mode) {} in TargetRegisterInfo()
641 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size; in getSubRegIdxSize()
647 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset; in getSubRegIdxOffset()
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| H A D | RegisterBankInfo.cpp | 58 unsigned HwMode) in RegisterBankInfo() argument
60 HwMode(HwMode) { in RegisterBankInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.h | 132 SystemZRegisterInfo(unsigned int RA, unsigned int HwMode);
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| H A D | SystemZRegisterInfo.cpp | 235 SystemZRegisterInfo::SystemZRegisterInfo(unsigned int RA, unsigned int HwMode) in SystemZRegisterInfo() argument
237 HwMode) {} in SystemZRegisterInfo()
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| H A D | SystemZFeatures.td | 199 def NoVecHwMode : HwMode<"-vector", [FeatureNoVector]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.h | 59 RISCVRegisterInfo(unsigned HwMode);
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| H A D | RISCVRegisterInfo.cpp | 57 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() argument
59 /*PC*/0, HwMode) {} in RISCVRegisterInfo()
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| H A D | RISCVRegisterInfo.td | 73 // GPR sizes change with HwMode.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 30 AArch64RegisterInfo(const Triple &TT, unsigned HwMode);
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| H A D | AArch64RegisterInfo.cpp | 43 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT, unsigned HwMode) in AArch64RegisterInfo() argument
44 : AArch64GenRegisterInfo(AArch64::LR, 0, 0, 0, HwMode), TT(TT) { in AArch64RegisterInfo()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 23 class HwMode<string FS, list<Predicate> Ps> {
39 def DefaultMode : HwMode<"", []>;
46 class HwModeSelect<list<HwMode> Ms, int ObjectsLength> {
47 list<HwMode> Modes = Ms;
58 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
85 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
96 class SubRegRangeByHwMode<list<HwMode> Ms = [], list<SubRegRange> Ts = []>
578 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
580 // to encode and decode based on HwMode.
581 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []>
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