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Searched refs:Hexagon (Results 1 – 25 of 112) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaHexagon.cpp38 { Hexagon::BI__builtin_circ_ldd, {{ 3, true, 4, 3 }} }, in CheckHexagonBuiltinArgument()
39 { Hexagon::BI__builtin_circ_ldw, {{ 3, true, 4, 2 }} }, in CheckHexagonBuiltinArgument()
40 { Hexagon::BI__builtin_circ_ldh, {{ 3, true, 4, 1 }} }, in CheckHexagonBuiltinArgument()
41 { Hexagon::BI__builtin_circ_lduh, {{ 3, true, 4, 1 }} }, in CheckHexagonBuiltinArgument()
42 { Hexagon::BI__builtin_circ_ldb, {{ 3, true, 4, 0 }} }, in CheckHexagonBuiltinArgument()
43 { Hexagon::BI__builtin_circ_ldub, {{ 3, true, 4, 0 }} }, in CheckHexagonBuiltinArgument()
44 { Hexagon::BI__builtin_circ_std, {{ 3, true, 4, 3 }} }, in CheckHexagonBuiltinArgument()
45 { Hexagon::BI__builtin_circ_stw, {{ 3, true, 4, 2 }} }, in CheckHexagonBuiltinArgument()
46 { Hexagon::BI__builtin_circ_sth, {{ 3, true, 4, 1 }} }, in CheckHexagonBuiltinArgument()
47 { Hexagon::BI__builtin_circ_sthhi, {{ 3, true, 4, 1 }} }, in CheckHexagonBuiltinArgument()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrIntrinsics.inc4 {Hexagon::A2_abs, Intrinsic::hexagon_A2_abs},
5 {Hexagon::A2_absp, Intrinsic::hexagon_A2_absp},
6 {Hexagon::A2_abssat, Intrinsic::hexagon_A2_abssat},
7 {Hexagon::A2_add, Intrinsic::hexagon_A2_add},
8 {Hexagon::A2_addh_h16_hh, Intrinsic::hexagon_A2_addh_h16_hh},
9 {Hexagon::A2_addh_h16_hl, Intrinsic::hexagon_A2_addh_h16_hl},
10 {Hexagon::A2_addh_h16_lh, Intrinsic::hexagon_A2_addh_h16_lh},
11 {Hexagon::A2_addh_h16_ll, Intrinsic::hexagon_A2_addh_h16_ll},
12 {Hexagon::A2_addh_h16_sat_hh, Intrinsic::hexagon_A2_addh_h16_sat_hh},
13 {Hexagon::A2_addh_h16_sat_hl, Intrinsic::hexagon_A2_addh_h16_sat_hl},
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H A DHexagonDepTimingClasses.h20 case Hexagon::Sched::tc_112d30d6: in is_TC1()
21 case Hexagon::Sched::tc_151bf368: in is_TC1()
22 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
23 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
24 case Hexagon::Sched::tc_23708a21: in is_TC1()
25 case Hexagon::Sched::tc_24f426ab: in is_TC1()
26 case Hexagon::Sched::tc_2f573607: in is_TC1()
27 case Hexagon::Sched::tc_388f9897: in is_TC1()
28 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
29 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
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H A DHexagonInstrInfo.cpp121 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
131 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
132 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
136 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
137 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
159 if (MI.getOpcode() == Hexagon::A2_tfrsi) { in isAsCheapAsAMove()
188 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR)) in shouldSink()
202 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
203 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
204 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
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H A DHexagonRegisterInfo.cpp52 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
57 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || in isEHReturnCalleeSaveReg()
58 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; in isEHReturnCalleeSaveReg()
64 using namespace Hexagon; in getCallerSavedRegs()
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
124 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, in getCalleeSavedRegs()
125 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
126 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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H A DHexagonAsmPrinter.cpp68 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
70 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
134 if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) in PrintAsmOperand()
136 Hexagon::isub_lo : in PrintAsmOperand()
137 Hexagon::isub_hi); in PrintAsmOperand()
270 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
276 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
277 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
284 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
289 case Hexagon::A2_tfrf: { in HexagonProcessInstruction()
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H A DHexagonNewValueJump.cpp148 if (!Hexagon::IntRegsRegClass.contains(Op.getReg())) in INITIALIZE_PASS_DEPENDENCY()
221 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
222 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
250 case Hexagon::C2_cmpeqi: in canCompareBeNewValueJump()
251 case Hexagon::C4_cmpneqi: in canCompareBeNewValueJump()
252 case Hexagon::C2_cmpgti: in canCompareBeNewValueJump()
253 case Hexagon::C4_cmpltei: in canCompareBeNewValueJump()
256 case Hexagon::C2_cmpgtui: in canCompareBeNewValueJump()
257 case Hexagon::C4_cmplteui: in canCompareBeNewValueJump()
260 case Hexagon::S2_tstbit_i: in canCompareBeNewValueJump()
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H A DHexagonDepArch.h16 namespace Hexagon {
35 inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) { in getCpu()
36 return StringSwitch<std::optional<Hexagon::ArchEnum>>(CPU) in getCpu()
37 .Case("generic", Hexagon::ArchEnum::V5) in getCpu()
38 .Case("hexagonv5", Hexagon::ArchEnum::V5) in getCpu()
39 .Case("hexagonv55", Hexagon::ArchEnum::V55) in getCpu()
40 .Case("hexagonv60", Hexagon::ArchEnum::V60) in getCpu()
41 .Case("hexagonv62", Hexagon::ArchEnum::V62) in getCpu()
42 .Case("hexagonv65", Hexagon::ArchEnum::V65) in getCpu()
43 .Case("hexagonv66", Hexagon::ArchEnum::V66) in getCpu()
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H A DHexagonSubtarget.h71 Hexagon::ArchEnum HexagonArchVersion;
72 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
148 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5; in hasV5Ops()
151 return getHexagonArchVersion() == Hexagon::ArchEnum::V5; in hasV5OpsOnly()
154 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55; in hasV55Ops()
157 return getHexagonArchVersion() == Hexagon::ArchEnum::V55; in hasV55OpsOnly()
160 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60; in hasV60Ops()
163 return getHexagonArchVersion() == Hexagon::ArchEnum::V60; in hasV60OpsOnly()
166 return getHexagonArchVersion() >= Hexagon::ArchEnum::V62; in hasV62Ops()
169 return getHexagonArchVersion() == Hexagon::ArchEnum::V62; in hasV62OpsOnly()
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H A DHexagonConstExtenders.cpp788 case Hexagon::S4_storeirbt_io: in isStoreImmediate()
789 case Hexagon::S4_storeirbf_io: in isStoreImmediate()
790 case Hexagon::S4_storeirht_io: in isStoreImmediate()
791 case Hexagon::S4_storeirhf_io: in isStoreImmediate()
792 case Hexagon::S4_storeirit_io: in isStoreImmediate()
793 case Hexagon::S4_storeirif_io: in isStoreImmediate()
794 case Hexagon::S4_storeirb_io: in isStoreImmediate()
795 case Hexagon::S4_storeirh_io: in isStoreImmediate()
796 case Hexagon::S4_storeiri_io: in isStoreImmediate()
806 case Hexagon::L2_loadrub_io: in isRegOffOpcode()
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H A DHexagonGenPredicate.cpp116 return RC == &Hexagon::PredRegsRegClass; in INITIALIZE_PASS_DEPENDENCY()
120 using namespace Hexagon; in getPredForm()
173 case Hexagon::C2_cmpeqi: in isConvertibleToPredForm()
174 case Hexagon::C4_cmpneqi: in isConvertibleToPredForm()
187 case Hexagon::C2_tfrpr: in collectPredicateGPR()
234 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) { in getPredRegFor()
244 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; in getPredRegFor()
264 case Hexagon::C2_cmpeq: in isScalarCmp()
265 case Hexagon::C2_cmpgt: in isScalarCmp()
266 case Hexagon::C2_cmpgtu: in isScalarCmp()
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H A DHexagonDepArch.td11 def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V…
13 …ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V…
15 …ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V…
17 …ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V…
19 …ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V…
21 …ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V…
23 …ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V…
25 …ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V68", "Enable Hexagon V…
27 …ArchV69: SubtargetFeature<"v69", "HexagonArchVersion", "Hexagon::ArchEnum::V69", "Enable Hexagon V…
29 …ArchV71: SubtargetFeature<"v71", "HexagonArchVersion", "Hexagon::ArchEnum::V71", "Enable Hexagon V…
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H A DHexagonVectorPrint.cpp66 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
67 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
68 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
69 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
73 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
78 return S[R-Hexagon::V0]; in getStringReg()
80 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
82 return S[R-Hexagon::Q0]; in getStringReg()
175 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
176 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
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H A DHexagonFrameLowering.cpp240 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) in getMax32BitSubRegister()
259 static_assert(Hexagon::R1 > 0, in getMaxCalleeSavedReg()
282 case Hexagon::PS_alloca: in needsStackFrame()
283 case Hexagon::PS_aligna: in needsStackFrame()
336 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r; in hasTailCall()
358 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in isRestoreCall()
359 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: in isRestoreCall()
360 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT: in isRestoreCall()
361 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC: in isRestoreCall()
362 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT: in isRestoreCall()
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H A DHexagonGenMemAbsolute.cpp87 if (Opc != Hexagon::CONST32 && Opc != Hexagon::A2_tfrsi) in runOnMachineFunction()
211 case Hexagon::L2_loadrb_io: in isValidIndexedLoad()
212 NewOpc = Hexagon::L4_loadrb_ap; in isValidIndexedLoad()
214 case Hexagon::L2_loadrh_io: in isValidIndexedLoad()
215 NewOpc = Hexagon::L4_loadrh_ap; in isValidIndexedLoad()
217 case Hexagon::L2_loadri_io: in isValidIndexedLoad()
218 NewOpc = Hexagon::L4_loadri_ap; in isValidIndexedLoad()
220 case Hexagon::L2_loadrd_io: in isValidIndexedLoad()
221 NewOpc = Hexagon::L4_loadrd_ap; in isValidIndexedLoad()
223 case Hexagon::L2_loadruh_io: in isValidIndexedLoad()
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H A DHexagonCFGOptimizer.cpp53 case Hexagon::J2_jumpt: in IsConditionalBranch()
54 case Hexagon::J2_jumptpt: in IsConditionalBranch()
55 case Hexagon::J2_jumpf: in IsConditionalBranch()
56 case Hexagon::J2_jumpfpt: in IsConditionalBranch()
57 case Hexagon::J2_jumptnew: in IsConditionalBranch()
58 case Hexagon::J2_jumpfnew: in IsConditionalBranch()
59 case Hexagon::J2_jumptnewpt: in IsConditionalBranch()
60 case Hexagon::J2_jumpfnewpt: in IsConditionalBranch()
67 return (Opc == Hexagon::J2_jump); in IsUnconditionalJump()
76 case Hexagon::J2_jumpt: in InvertAndChangeJumpTarget()
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H A DHexagonConstPropagation.cpp1950 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1951 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
1976 case Hexagon::A2_tfrsi: in evaluate()
1977 case Hexagon::A2_tfrpi: in evaluate()
1978 case Hexagon::CONST32: in evaluate()
1979 case Hexagon::CONST64: in evaluate()
2000 case Hexagon::PS_true: in evaluate()
2001 case Hexagon::PS_false: in evaluate()
2004 bool NonZero = (Opc == Hexagon::PS_true); in evaluate()
2012 case Hexagon::A2_and: in evaluate()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp36 using namespace Hexagon;
201 CurrentBundle->setOpcode(Hexagon::BUNDLE); in makeBundle()
280 case Hexagon::S2_allocframe: in remapInstruction()
281 if (MI.getOperand(0).getReg() == Hexagon::R29) { in remapInstruction()
282 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
287 case Hexagon::L2_deallocframe: in remapInstruction()
288 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
289 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
295 case Hexagon::L4_return: in remapInstruction()
296 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp30 using namespace Hexagon;
200 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
217 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
237 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
238 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
248 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
258 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
269 case Hexagon::L4_return: in getDuplexCandidateGroup()
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H A DHexagonMCELFStreamer.cpp68 assert(MCB.getOpcode() == Hexagon::BUNDLE); in emitInstruction()
154 case Hexagon::ArchV5: in featureToArchVersion()
156 case Hexagon::ArchV55: in featureToArchVersion()
158 case Hexagon::ArchV60: in featureToArchVersion()
159 case Hexagon::ExtensionHVXV60: in featureToArchVersion()
161 case Hexagon::ArchV62: in featureToArchVersion()
162 case Hexagon::ExtensionHVXV62: in featureToArchVersion()
164 case Hexagon::ArchV65: in featureToArchVersion()
165 case Hexagon::ExtensionHVXV65: in featureToArchVersion()
167 case Hexagon::ArchV66: in featureToArchVersion()
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H A DHexagonMCCompound.cpp26 using namespace Hexagon;
92 case Hexagon::C2_cmpeq: in getCompoundCandidateGroup()
93 case Hexagon::C2_cmpgt: in getCompoundCandidateGroup()
94 case Hexagon::C2_cmpgtu: in getCompoundCandidateGroup()
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
105 case Hexagon::C2_cmpeqi: in getCompoundCandidateGroup()
106 case Hexagon::C2_cmpgti: in getCompoundCandidateGroup()
107 case Hexagon::C2_cmpgtui: in getCompoundCandidateGroup()
113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
119 case Hexagon::A2_tfr: in getCompoundCandidateGroup()
[all …]
H A DHexagonMCInstrInfo.cpp36 return Register != Hexagon::NoRegister; in isPredicated()
39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator()
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator()
50 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() { in operator ++()
71 MCInst const &Hexagon::PacketIterator::operator*() const { in operator *()
77 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const { in operator ==()
102 iterator_range<Hexagon::PacketIterator>
106 return make_range(Hexagon::PacketIterator(MCII, MCI), in bundleInstructions()
107 Hexagon::PacketIterator(MCII, MCI, nullptr)); in bundleInstructions()
141 (STI.hasFeature(Hexagon::FeatureDuplex)) in canonicalizePacketImpl()
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H A DHexagonMCChecker.cpp37 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
41 ReadOnly.insert(Hexagon::PC); in init()
42 ReadOnly.insert(Hexagon::C9_8); in init()
46 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
47 Defs[Hexagon::LC0].insert(Unconditional); in init()
50 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
51 Defs[Hexagon::LC1].insert(Unconditional); in init()
106 STI.hasFeature(Hexagon::ArchV69); in init()
110 if (Hexagon::R31 != R && MCID.isCall()) in init()
114 if (Hexagon::PC == R) in init()
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H A DHexagonMCTargetDesc.cpp101 static cl::opt<Hexagon::ArchEnum> EnableHVX(
103 cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
104 clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
105 clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
106 clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
107 clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
108 clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
109 clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
110 clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"),
111 clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"),
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DHexagon.cpp30 { Hexagon::BI__builtin_HEXAGON_##x, Intrinsic::hexagon_##x, s }, in getIntrinsicForHexagonNonClangBuiltin()
166 case Hexagon::BI__builtin_HEXAGON_V6_vaddcarry: in EmitHexagonBuiltinExpr()
167 case Hexagon::BI__builtin_HEXAGON_V6_vaddcarry_128B: in EmitHexagonBuiltinExpr()
168 case Hexagon::BI__builtin_HEXAGON_V6_vsubcarry: in EmitHexagonBuiltinExpr()
169 case Hexagon::BI__builtin_HEXAGON_V6_vsubcarry_128B: { in EmitHexagonBuiltinExpr()
186 case Hexagon::BI__builtin_HEXAGON_V6_vaddcarryo: in EmitHexagonBuiltinExpr()
187 case Hexagon::BI__builtin_HEXAGON_V6_vaddcarryo_128B: in EmitHexagonBuiltinExpr()
188 case Hexagon::BI__builtin_HEXAGON_V6_vsubcarryo: in EmitHexagonBuiltinExpr()
189 case Hexagon::BI__builtin_HEXAGON_V6_vsubcarryo_128B: { in EmitHexagonBuiltinExpr()
203 case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstoreq: in EmitHexagonBuiltinExpr()
[all …]

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