Lines Matching refs:Hexagon
123 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
133 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
134 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
138 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
139 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
161 if (MI.getOpcode() == Hexagon::A2_tfrsi) { in isAsCheapAsAMove()
190 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR)) in shouldSink()
204 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
205 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
206 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
208 LOOPi = Hexagon::J2_loop1i; in findLoopInstr()
209 LOOPr = Hexagon::J2_loop1r; in findLoopInstr()
295 case Hexagon::L2_loadri_io: in isLoadFromStackSlot()
296 case Hexagon::L2_loadrd_io: in isLoadFromStackSlot()
297 case Hexagon::V6_vL32b_ai: in isLoadFromStackSlot()
298 case Hexagon::V6_vL32b_nt_ai: in isLoadFromStackSlot()
299 case Hexagon::V6_vL32Ub_ai: in isLoadFromStackSlot()
300 case Hexagon::LDriw_pred: in isLoadFromStackSlot()
301 case Hexagon::LDriw_ctr: in isLoadFromStackSlot()
302 case Hexagon::PS_vloadrq_ai: in isLoadFromStackSlot()
303 case Hexagon::PS_vloadrw_ai: in isLoadFromStackSlot()
304 case Hexagon::PS_vloadrw_nt_ai: { in isLoadFromStackSlot()
315 case Hexagon::L2_ploadrit_io: in isLoadFromStackSlot()
316 case Hexagon::L2_ploadrif_io: in isLoadFromStackSlot()
317 case Hexagon::L2_ploadrdt_io: in isLoadFromStackSlot()
318 case Hexagon::L2_ploadrdf_io: { in isLoadFromStackSlot()
343 case Hexagon::S2_storerb_io: in isStoreToStackSlot()
344 case Hexagon::S2_storerh_io: in isStoreToStackSlot()
345 case Hexagon::S2_storeri_io: in isStoreToStackSlot()
346 case Hexagon::S2_storerd_io: in isStoreToStackSlot()
347 case Hexagon::V6_vS32b_ai: in isStoreToStackSlot()
348 case Hexagon::V6_vS32Ub_ai: in isStoreToStackSlot()
349 case Hexagon::STriw_pred: in isStoreToStackSlot()
350 case Hexagon::STriw_ctr: in isStoreToStackSlot()
351 case Hexagon::PS_vstorerq_ai: in isStoreToStackSlot()
352 case Hexagon::PS_vstorerw_ai: { in isStoreToStackSlot()
363 case Hexagon::S2_pstorerbt_io: in isStoreToStackSlot()
364 case Hexagon::S2_pstorerbf_io: in isStoreToStackSlot()
365 case Hexagon::S2_pstorerht_io: in isStoreToStackSlot()
366 case Hexagon::S2_pstorerhf_io: in isStoreToStackSlot()
367 case Hexagon::S2_pstorerit_io: in isStoreToStackSlot()
368 case Hexagon::S2_pstorerif_io: in isStoreToStackSlot()
369 case Hexagon::S2_pstorerdt_io: in isStoreToStackSlot()
370 case Hexagon::S2_pstorerdf_io: { in isStoreToStackSlot()
478 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump && in analyzeBranch()
514 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB()) in analyzeBranch()
516 if (SecLastOpcode == Hexagon::J2_jump && in analyzeBranch()
528 if (LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
560 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) { in analyzeBranch()
573 (LastOpcode == Hexagon::J2_jump)) { in analyzeBranch()
584 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
593 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
620 if (Count && (I->getOpcode() == Hexagon::J2_jump)) in removeBranch()
635 unsigned BOpc = Hexagon::J2_jump; in insertBranch()
636 unsigned BccOpc = Hexagon::J2_jumpt; in insertBranch()
744 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r in HexagonPipelinerLoopInfo()
763 TII->get(Hexagon::C2_cmpgtui), Done) in createTripCountGreaterCondition()
766 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf)); in createTripCountGreaterCondition()
782 if (Loop->getOpcode() == Hexagon::J2_loop0i || in adjustTripCount()
783 Loop->getOpcode() == Hexagon::J2_loop1i) { in adjustTripCount()
795 TII->get(Hexagon::A2_addi), NewLoopCount) in adjustTripCount()
864 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
865 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg) in copyPhysReg()
869 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
870 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg) in copyPhysReg()
874 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
876 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg) in copyPhysReg()
880 if (Hexagon::CtrRegsRegClass.contains(DestReg) && in copyPhysReg()
881 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
882 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg) in copyPhysReg()
886 if (Hexagon::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
887 Hexagon::CtrRegsRegClass.contains(SrcReg)) { in copyPhysReg()
888 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg) in copyPhysReg()
892 if (Hexagon::ModRegsRegClass.contains(DestReg) && in copyPhysReg()
893 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
894 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg) in copyPhysReg()
898 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
899 Hexagon::IntRegsRegClass.contains(DestReg)) { in copyPhysReg()
900 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg) in copyPhysReg()
904 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in copyPhysReg()
905 Hexagon::PredRegsRegClass.contains(DestReg)) { in copyPhysReg()
906 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg) in copyPhysReg()
910 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
911 Hexagon::IntRegsRegClass.contains(DestReg)) { in copyPhysReg()
912 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg) in copyPhysReg()
916 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
917 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg). in copyPhysReg()
921 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
925 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
928 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg) in copyPhysReg()
933 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
934 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg) in copyPhysReg()
939 if (Hexagon::HvxQRRegClass.contains(SrcReg) && in copyPhysReg()
940 Hexagon::HvxVRRegClass.contains(DestReg)) { in copyPhysReg()
944 if (Hexagon::HvxQRRegClass.contains(DestReg) && in copyPhysReg()
945 Hexagon::HvxVRRegClass.contains(SrcReg)) { in copyPhysReg()
973 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
974 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) in storeRegToStackSlot()
977 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
978 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io)) in storeRegToStackSlot()
981 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
982 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) in storeRegToStackSlot()
985 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
986 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr)) in storeRegToStackSlot()
989 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
990 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai)) in storeRegToStackSlot()
993 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
994 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai)) in storeRegToStackSlot()
997 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
998 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai)) in storeRegToStackSlot()
1020 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1021 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg) in loadRegFromStackSlot()
1023 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1024 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg) in loadRegFromStackSlot()
1026 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1027 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) in loadRegFromStackSlot()
1029 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1030 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg) in loadRegFromStackSlot()
1032 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1033 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg) in loadRegFromStackSlot()
1035 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1036 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg) in loadRegFromStackSlot()
1038 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1039 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg) in loadRegFromStackSlot()
1063 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
1064 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx) in expandPostRAPseudo()
1084 case Hexagon::PS_call_instrprof_custom: { in expandPostRAPseudo()
1095 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrsi), Hexagon::R0) in expandPostRAPseudo()
1109 auto MIB = BuildMI(MBB, MI, DL, get(Hexagon::J2_call)) in expandPostRAPseudo()
1110 .addUse(Hexagon::R0, RegState::Implicit|RegState::InternalRead) in expandPostRAPseudo()
1111 .addDef(Hexagon::R29, RegState::ImplicitDefine) in expandPostRAPseudo()
1112 .addDef(Hexagon::R30, RegState::ImplicitDefine) in expandPostRAPseudo()
1113 .addDef(Hexagon::R14, RegState::ImplicitDefine) in expandPostRAPseudo()
1114 .addDef(Hexagon::R15, RegState::ImplicitDefine) in expandPostRAPseudo()
1115 .addDef(Hexagon::R28, RegState::ImplicitDefine); in expandPostRAPseudo()
1132 case Hexagon::PS_aligna: in expandPostRAPseudo()
1133 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1138 case Hexagon::V6_vassignp: { in expandPostRAPseudo()
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1142 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1147 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg) in expandPostRAPseudo()
1153 case Hexagon::V6_lo: { in expandPostRAPseudo()
1156 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1162 case Hexagon::V6_hi: { in expandPostRAPseudo()
1165 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1171 case Hexagon::PS_vloadrv_ai: { in expandPostRAPseudo()
1176 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1177 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1178 : Hexagon::V6_vL32Ub_ai; in expandPostRAPseudo()
1186 case Hexagon::PS_vloadrw_ai: { in expandPostRAPseudo()
1191 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1192 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1193 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1194 : Hexagon::V6_vL32Ub_ai; in expandPostRAPseudo()
1196 HRI.getSubReg(DstReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1201 HRI.getSubReg(DstReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1208 case Hexagon::PS_vstorerv_ai: { in expandPostRAPseudo()
1214 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1215 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1216 : Hexagon::V6_vS32Ub_ai; in expandPostRAPseudo()
1225 case Hexagon::PS_vstorerw_ai: { in expandPostRAPseudo()
1230 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1231 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1232 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1233 : Hexagon::V6_vS32Ub_ai; in expandPostRAPseudo()
1237 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1242 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1247 case Hexagon::PS_true: { in expandPostRAPseudo()
1249 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg) in expandPostRAPseudo()
1255 case Hexagon::PS_false: { in expandPostRAPseudo()
1257 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg) in expandPostRAPseudo()
1263 case Hexagon::PS_qtrue: { in expandPostRAPseudo()
1264 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1265 .addReg(Hexagon::V0, RegState::Undef) in expandPostRAPseudo()
1266 .addReg(Hexagon::V0, RegState::Undef); in expandPostRAPseudo()
1270 case Hexagon::PS_qfalse: { in expandPostRAPseudo()
1271 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1272 .addReg(Hexagon::V0, RegState::Undef) in expandPostRAPseudo()
1273 .addReg(Hexagon::V0, RegState::Undef); in expandPostRAPseudo()
1277 case Hexagon::PS_vdd0: { in expandPostRAPseudo()
1279 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1285 case Hexagon::PS_vmulw: { in expandPostRAPseudo()
1290 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1291 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1292 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1293 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1294 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi), in expandPostRAPseudo()
1295 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1298 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi), in expandPostRAPseudo()
1299 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1309 case Hexagon::PS_vmulw_acc: { in expandPostRAPseudo()
1315 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1316 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1317 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1318 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1319 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1320 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1321 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci), in expandPostRAPseudo()
1322 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1326 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci), in expandPostRAPseudo()
1327 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1340 case Hexagon::PS_pselect: { in expandPostRAPseudo()
1354 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd) in expandPostRAPseudo()
1358 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd) in expandPostRAPseudo()
1364 case Hexagon::PS_vselect: { in expandPostRAPseudo()
1378 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov)) in expandPostRAPseudo()
1387 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov)) in expandPostRAPseudo()
1397 case Hexagon::PS_wselect: { in expandPostRAPseudo()
1411 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1412 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1413 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine)) in expandPostRAPseudo()
1423 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1424 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1425 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine)) in expandPostRAPseudo()
1437 case Hexagon::PS_crash: { in expandPostRAPseudo()
1463 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13) in expandPostRAPseudo()
1470 case Hexagon::PS_tailcall_i: in expandPostRAPseudo()
1471 MI.setDesc(get(Hexagon::J2_jump)); in expandPostRAPseudo()
1473 case Hexagon::PS_tailcall_r: in expandPostRAPseudo()
1474 case Hexagon::PS_jmpret: in expandPostRAPseudo()
1475 MI.setDesc(get(Hexagon::J2_jumpr)); in expandPostRAPseudo()
1477 case Hexagon::PS_jmprett: in expandPostRAPseudo()
1478 MI.setDesc(get(Hexagon::J2_jumprt)); in expandPostRAPseudo()
1480 case Hexagon::PS_jmpretf: in expandPostRAPseudo()
1481 MI.setDesc(get(Hexagon::J2_jumprf)); in expandPostRAPseudo()
1483 case Hexagon::PS_jmprettnewpt: in expandPostRAPseudo()
1484 MI.setDesc(get(Hexagon::J2_jumprtnewpt)); in expandPostRAPseudo()
1486 case Hexagon::PS_jmpretfnewpt: in expandPostRAPseudo()
1487 MI.setDesc(get(Hexagon::J2_jumprfnewpt)); in expandPostRAPseudo()
1489 case Hexagon::PS_jmprettnew: in expandPostRAPseudo()
1490 MI.setDesc(get(Hexagon::J2_jumprtnew)); in expandPostRAPseudo()
1492 case Hexagon::PS_jmpretfnew: in expandPostRAPseudo()
1493 MI.setDesc(get(Hexagon::J2_jumprfnew)); in expandPostRAPseudo()
1496 case Hexagon::PS_loadrub_pci: in expandPostRAPseudo()
1497 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1498 case Hexagon::PS_loadrb_pci: in expandPostRAPseudo()
1499 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1500 case Hexagon::PS_loadruh_pci: in expandPostRAPseudo()
1501 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1502 case Hexagon::PS_loadrh_pci: in expandPostRAPseudo()
1503 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1504 case Hexagon::PS_loadri_pci: in expandPostRAPseudo()
1505 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1506 case Hexagon::PS_loadrd_pci: in expandPostRAPseudo()
1507 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1508 case Hexagon::PS_loadrub_pcr: in expandPostRAPseudo()
1509 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1510 case Hexagon::PS_loadrb_pcr: in expandPostRAPseudo()
1511 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1512 case Hexagon::PS_loadruh_pcr: in expandPostRAPseudo()
1513 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1514 case Hexagon::PS_loadrh_pcr: in expandPostRAPseudo()
1515 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1516 case Hexagon::PS_loadri_pcr: in expandPostRAPseudo()
1517 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1518 case Hexagon::PS_loadrd_pcr: in expandPostRAPseudo()
1519 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1520 case Hexagon::PS_storerb_pci: in expandPostRAPseudo()
1521 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1522 case Hexagon::PS_storerh_pci: in expandPostRAPseudo()
1523 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1524 case Hexagon::PS_storerf_pci: in expandPostRAPseudo()
1525 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1526 case Hexagon::PS_storeri_pci: in expandPostRAPseudo()
1527 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1528 case Hexagon::PS_storerd_pci: in expandPostRAPseudo()
1529 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1530 case Hexagon::PS_storerb_pcr: in expandPostRAPseudo()
1531 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1532 case Hexagon::PS_storerh_pcr: in expandPostRAPseudo()
1533 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1534 case Hexagon::PS_storerf_pcr: in expandPostRAPseudo()
1535 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1536 case Hexagon::PS_storeri_pcr: in expandPostRAPseudo()
1537 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1538 case Hexagon::PS_storerd_pcr: in expandPostRAPseudo()
1539 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1553 case Hexagon::V6_vgathermh_pseudo: in expandVGatherPseudo()
1554 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh)) in expandVGatherPseudo()
1558 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1561 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1565 case Hexagon::V6_vgathermw_pseudo: in expandVGatherPseudo()
1566 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw)) in expandVGatherPseudo()
1570 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1573 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1577 case Hexagon::V6_vgathermhw_pseudo: in expandVGatherPseudo()
1578 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw)) in expandVGatherPseudo()
1582 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1585 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1589 case Hexagon::V6_vgathermhq_pseudo: in expandVGatherPseudo()
1590 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq)) in expandVGatherPseudo()
1595 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1598 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1602 case Hexagon::V6_vgathermwq_pseudo: in expandVGatherPseudo()
1603 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq)) in expandVGatherPseudo()
1608 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1611 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1615 case Hexagon::V6_vgathermhwq_pseudo: in expandVGatherPseudo()
1616 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq)) in expandVGatherPseudo()
1621 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1624 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1652 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop)); in insertNoop()
1740 if (RC == &Hexagon::PredRegsRegClass) { in ClobbersPredicate()
1746 for (Register PR : Hexagon::PredRegsRegClass) { in ClobbersPredicate()
1769 case Hexagon::V6_vL32b_ai: in isPredicable()
1770 case Hexagon::V6_vL32b_pi: in isPredicable()
1771 case Hexagon::V6_vL32b_ppu: in isPredicable()
1772 case Hexagon::V6_vL32b_cur_ai: in isPredicable()
1773 case Hexagon::V6_vL32b_cur_pi: in isPredicable()
1774 case Hexagon::V6_vL32b_cur_ppu: in isPredicable()
1775 case Hexagon::V6_vL32b_nt_ai: in isPredicable()
1776 case Hexagon::V6_vL32b_nt_pi: in isPredicable()
1777 case Hexagon::V6_vL32b_nt_ppu: in isPredicable()
1778 case Hexagon::V6_vL32b_tmp_ai: in isPredicable()
1779 case Hexagon::V6_vL32b_tmp_pi: in isPredicable()
1780 case Hexagon::V6_vL32b_tmp_ppu: in isPredicable()
1781 case Hexagon::V6_vL32b_nt_cur_ai: in isPredicable()
1782 case Hexagon::V6_vL32b_nt_cur_pi: in isPredicable()
1783 case Hexagon::V6_vL32b_nt_cur_ppu: in isPredicable()
1784 case Hexagon::V6_vL32b_nt_tmp_ai: in isPredicable()
1785 case Hexagon::V6_vL32b_nt_tmp_pi: in isPredicable()
1786 case Hexagon::V6_vL32b_nt_tmp_ppu: in isPredicable()
1887 case Hexagon::C2_cmpeq: in analyzeCompare()
1888 case Hexagon::C2_cmpeqp: in analyzeCompare()
1889 case Hexagon::C2_cmpgt: in analyzeCompare()
1890 case Hexagon::C2_cmpgtp: in analyzeCompare()
1891 case Hexagon::C2_cmpgtu: in analyzeCompare()
1892 case Hexagon::C2_cmpgtup: in analyzeCompare()
1893 case Hexagon::C4_cmpneq: in analyzeCompare()
1894 case Hexagon::C4_cmplte: in analyzeCompare()
1895 case Hexagon::C4_cmplteu: in analyzeCompare()
1896 case Hexagon::C2_cmpeqi: in analyzeCompare()
1897 case Hexagon::C2_cmpgti: in analyzeCompare()
1898 case Hexagon::C2_cmpgtui: in analyzeCompare()
1899 case Hexagon::C4_cmpneqi: in analyzeCompare()
1900 case Hexagon::C4_cmplteui: in analyzeCompare()
1901 case Hexagon::C4_cmpltei: in analyzeCompare()
1905 case Hexagon::A4_cmpbeq: in analyzeCompare()
1906 case Hexagon::A4_cmpbgt: in analyzeCompare()
1907 case Hexagon::A4_cmpbgtu: in analyzeCompare()
1908 case Hexagon::A4_cmpbeqi: in analyzeCompare()
1909 case Hexagon::A4_cmpbgti: in analyzeCompare()
1910 case Hexagon::A4_cmpbgtui: in analyzeCompare()
1914 case Hexagon::A4_cmpheq: in analyzeCompare()
1915 case Hexagon::A4_cmphgt: in analyzeCompare()
1916 case Hexagon::A4_cmphgtu: in analyzeCompare()
1917 case Hexagon::A4_cmpheqi: in analyzeCompare()
1918 case Hexagon::A4_cmphgti: in analyzeCompare()
1919 case Hexagon::A4_cmphgtui: in analyzeCompare()
1927 case Hexagon::C2_cmpeq: in analyzeCompare()
1928 case Hexagon::C2_cmpeqp: in analyzeCompare()
1929 case Hexagon::C2_cmpgt: in analyzeCompare()
1930 case Hexagon::C2_cmpgtp: in analyzeCompare()
1931 case Hexagon::C2_cmpgtu: in analyzeCompare()
1932 case Hexagon::C2_cmpgtup: in analyzeCompare()
1933 case Hexagon::A4_cmpbeq: in analyzeCompare()
1934 case Hexagon::A4_cmpbgt: in analyzeCompare()
1935 case Hexagon::A4_cmpbgtu: in analyzeCompare()
1936 case Hexagon::A4_cmpheq: in analyzeCompare()
1937 case Hexagon::A4_cmphgt: in analyzeCompare()
1938 case Hexagon::A4_cmphgtu: in analyzeCompare()
1939 case Hexagon::C4_cmpneq: in analyzeCompare()
1940 case Hexagon::C4_cmplte: in analyzeCompare()
1941 case Hexagon::C4_cmplteu: in analyzeCompare()
1946 case Hexagon::C2_cmpeqi: in analyzeCompare()
1947 case Hexagon::C2_cmpgtui: in analyzeCompare()
1948 case Hexagon::C2_cmpgti: in analyzeCompare()
1949 case Hexagon::C4_cmpneqi: in analyzeCompare()
1950 case Hexagon::C4_cmplteui: in analyzeCompare()
1951 case Hexagon::C4_cmpltei: in analyzeCompare()
1952 case Hexagon::A4_cmpbeqi: in analyzeCompare()
1953 case Hexagon::A4_cmpbgti: in analyzeCompare()
1954 case Hexagon::A4_cmpbgtui: in analyzeCompare()
1955 case Hexagon::A4_cmpheqi: in analyzeCompare()
1956 case Hexagon::A4_cmphgti: in analyzeCompare()
1957 case Hexagon::A4_cmphgtui: { in analyzeCompare()
2055 } else if (MI.getOpcode() == Hexagon::A2_addi) { in getIncrementValue()
2105 TRC = &Hexagon::PredRegsRegClass; in createVR()
2107 TRC = &Hexagon::IntRegsRegClass; in createVR()
2109 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
2134 MI.getDesc().getOpcode() != Hexagon::S2_allocframe && in isComplex()
2135 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe && in isComplex()
2197 case Hexagon::L4_return: in isDeallocRet()
2198 case Hexagon::L4_return_t: in isDeallocRet()
2199 case Hexagon::L4_return_f: in isDeallocRet()
2200 case Hexagon::L4_return_tnew_pnt: in isDeallocRet()
2201 case Hexagon::L4_return_fnew_pnt: in isDeallocRet()
2202 case Hexagon::L4_return_tnew_pt: in isDeallocRet()
2203 case Hexagon::L4_return_fnew_pt: in isDeallocRet()
2243 case Hexagon::V6_vL32b_cur_pi: in isDotCurInst()
2244 case Hexagon::V6_vL32b_cur_ai: in isDotCurInst()
2268 return (Opcode == Hexagon::ENDLOOP0 || in isEndLoopN()
2269 Opcode == Hexagon::ENDLOOP1); in isEndLoopN()
2296 case Hexagon::PS_fi: in isExtendable()
2297 case Hexagon::PS_fia: in isExtendable()
2339 case Hexagon::J2_callr: in isIndirectCall()
2340 case Hexagon::J2_callrf: in isIndirectCall()
2341 case Hexagon::J2_callrt: in isIndirectCall()
2342 case Hexagon::PS_call_nr: in isIndirectCall()
2350 case Hexagon::L4_return: in isIndirectL4Return()
2351 case Hexagon::L4_return_t: in isIndirectL4Return()
2352 case Hexagon::L4_return_f: in isIndirectL4Return()
2353 case Hexagon::L4_return_fnew_pnt: in isIndirectL4Return()
2354 case Hexagon::L4_return_fnew_pt: in isIndirectL4Return()
2355 case Hexagon::L4_return_tnew_pnt: in isIndirectL4Return()
2356 case Hexagon::L4_return_tnew_pt: in isIndirectL4Return()
2364 case Hexagon::J2_jumpr: in isJumpR()
2365 case Hexagon::J2_jumprt: in isJumpR()
2366 case Hexagon::J2_jumprf: in isJumpR()
2367 case Hexagon::J2_jumprtnewpt: in isJumpR()
2368 case Hexagon::J2_jumprfnewpt: in isJumpR()
2369 case Hexagon::J2_jumprtnew: in isJumpR()
2370 case Hexagon::J2_jumprfnew: in isJumpR()
2391 case Hexagon::J2_jump: // bits<24> dst; // r22:2 in isJumpWithinBranchRange()
2392 case Hexagon::J2_call: in isJumpWithinBranchRange()
2393 case Hexagon::PS_call_nr: in isJumpWithinBranchRange()
2395 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2 in isJumpWithinBranchRange()
2396 case Hexagon::J2_jumpf: in isJumpWithinBranchRange()
2397 case Hexagon::J2_jumptnew: in isJumpWithinBranchRange()
2398 case Hexagon::J2_jumptnewpt: in isJumpWithinBranchRange()
2399 case Hexagon::J2_jumpfnew: in isJumpWithinBranchRange()
2400 case Hexagon::J2_jumpfnewpt: in isJumpWithinBranchRange()
2401 case Hexagon::J2_callt: in isJumpWithinBranchRange()
2402 case Hexagon::J2_callf: in isJumpWithinBranchRange()
2404 case Hexagon::J2_loop0i: in isJumpWithinBranchRange()
2405 case Hexagon::J2_loop0iext: in isJumpWithinBranchRange()
2406 case Hexagon::J2_loop0r: in isJumpWithinBranchRange()
2407 case Hexagon::J2_loop0rext: in isJumpWithinBranchRange()
2408 case Hexagon::J2_loop1i: in isJumpWithinBranchRange()
2409 case Hexagon::J2_loop1iext: in isJumpWithinBranchRange()
2410 case Hexagon::J2_loop1r: in isJumpWithinBranchRange()
2411 case Hexagon::J2_loop1rext: in isJumpWithinBranchRange()
2414 case Hexagon::J4_cmpeqi_tp0_jump_nt: in isJumpWithinBranchRange()
2415 case Hexagon::J4_cmpeqi_tp1_jump_nt: in isJumpWithinBranchRange()
2416 case Hexagon::J4_cmpeqn1_tp0_jump_nt: in isJumpWithinBranchRange()
2417 case Hexagon::J4_cmpeqn1_tp1_jump_nt: in isJumpWithinBranchRange()
2430 return Opcode == Hexagon::J2_loop0i || in isLoopN()
2431 Opcode == Hexagon::J2_loop0r || in isLoopN()
2432 Opcode == Hexagon::J2_loop0iext || in isLoopN()
2433 Opcode == Hexagon::J2_loop0rext || in isLoopN()
2434 Opcode == Hexagon::J2_loop1i || in isLoopN()
2435 Opcode == Hexagon::J2_loop1r || in isLoopN()
2436 Opcode == Hexagon::J2_loop1iext || in isLoopN()
2437 Opcode == Hexagon::J2_loop1rext; in isLoopN()
2443 case Hexagon::L4_iadd_memopw_io: in isMemOp()
2444 case Hexagon::L4_isub_memopw_io: in isMemOp()
2445 case Hexagon::L4_add_memopw_io: in isMemOp()
2446 case Hexagon::L4_sub_memopw_io: in isMemOp()
2447 case Hexagon::L4_and_memopw_io: in isMemOp()
2448 case Hexagon::L4_or_memopw_io: in isMemOp()
2449 case Hexagon::L4_iadd_memoph_io: in isMemOp()
2450 case Hexagon::L4_isub_memoph_io: in isMemOp()
2451 case Hexagon::L4_add_memoph_io: in isMemOp()
2452 case Hexagon::L4_sub_memoph_io: in isMemOp()
2453 case Hexagon::L4_and_memoph_io: in isMemOp()
2454 case Hexagon::L4_or_memoph_io: in isMemOp()
2455 case Hexagon::L4_iadd_memopb_io: in isMemOp()
2456 case Hexagon::L4_isub_memopb_io: in isMemOp()
2457 case Hexagon::L4_add_memopb_io: in isMemOp()
2458 case Hexagon::L4_sub_memopb_io: in isMemOp()
2459 case Hexagon::L4_and_memopb_io: in isMemOp()
2460 case Hexagon::L4_or_memopb_io: in isMemOp()
2461 case Hexagon::L4_ior_memopb_io: in isMemOp()
2462 case Hexagon::L4_ior_memoph_io: in isMemOp()
2463 case Hexagon::L4_ior_memopw_io: in isMemOp()
2464 case Hexagon::L4_iand_memopb_io: in isMemOp()
2465 case Hexagon::L4_iand_memoph_io: in isMemOp()
2466 case Hexagon::L4_iand_memopw_io: in isMemOp()
2556 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 || in isSaveCalleeSavedRegsCall()
2557 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT || in isSaveCalleeSavedRegsCall()
2558 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC || in isSaveCalleeSavedRegsCall()
2559 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC; in isSaveCalleeSavedRegsCall()
2565 case Hexagon::L2_loadrb_io: in isSignExtendingLoad()
2566 case Hexagon::L4_loadrb_ur: in isSignExtendingLoad()
2567 case Hexagon::L4_loadrb_ap: in isSignExtendingLoad()
2568 case Hexagon::L2_loadrb_pr: in isSignExtendingLoad()
2569 case Hexagon::L2_loadrb_pbr: in isSignExtendingLoad()
2570 case Hexagon::L2_loadrb_pi: in isSignExtendingLoad()
2571 case Hexagon::L2_loadrb_pci: in isSignExtendingLoad()
2572 case Hexagon::L2_loadrb_pcr: in isSignExtendingLoad()
2573 case Hexagon::L2_loadbsw2_io: in isSignExtendingLoad()
2574 case Hexagon::L4_loadbsw2_ur: in isSignExtendingLoad()
2575 case Hexagon::L4_loadbsw2_ap: in isSignExtendingLoad()
2576 case Hexagon::L2_loadbsw2_pr: in isSignExtendingLoad()
2577 case Hexagon::L2_loadbsw2_pbr: in isSignExtendingLoad()
2578 case Hexagon::L2_loadbsw2_pi: in isSignExtendingLoad()
2579 case Hexagon::L2_loadbsw2_pci: in isSignExtendingLoad()
2580 case Hexagon::L2_loadbsw2_pcr: in isSignExtendingLoad()
2581 case Hexagon::L2_loadbsw4_io: in isSignExtendingLoad()
2582 case Hexagon::L4_loadbsw4_ur: in isSignExtendingLoad()
2583 case Hexagon::L4_loadbsw4_ap: in isSignExtendingLoad()
2584 case Hexagon::L2_loadbsw4_pr: in isSignExtendingLoad()
2585 case Hexagon::L2_loadbsw4_pbr: in isSignExtendingLoad()
2586 case Hexagon::L2_loadbsw4_pi: in isSignExtendingLoad()
2587 case Hexagon::L2_loadbsw4_pci: in isSignExtendingLoad()
2588 case Hexagon::L2_loadbsw4_pcr: in isSignExtendingLoad()
2589 case Hexagon::L4_loadrb_rr: in isSignExtendingLoad()
2590 case Hexagon::L2_ploadrbt_io: in isSignExtendingLoad()
2591 case Hexagon::L2_ploadrbt_pi: in isSignExtendingLoad()
2592 case Hexagon::L2_ploadrbf_io: in isSignExtendingLoad()
2593 case Hexagon::L2_ploadrbf_pi: in isSignExtendingLoad()
2594 case Hexagon::L2_ploadrbtnew_io: in isSignExtendingLoad()
2595 case Hexagon::L2_ploadrbfnew_io: in isSignExtendingLoad()
2596 case Hexagon::L4_ploadrbt_rr: in isSignExtendingLoad()
2597 case Hexagon::L4_ploadrbf_rr: in isSignExtendingLoad()
2598 case Hexagon::L4_ploadrbtnew_rr: in isSignExtendingLoad()
2599 case Hexagon::L4_ploadrbfnew_rr: in isSignExtendingLoad()
2600 case Hexagon::L2_ploadrbtnew_pi: in isSignExtendingLoad()
2601 case Hexagon::L2_ploadrbfnew_pi: in isSignExtendingLoad()
2602 case Hexagon::L4_ploadrbt_abs: in isSignExtendingLoad()
2603 case Hexagon::L4_ploadrbf_abs: in isSignExtendingLoad()
2604 case Hexagon::L4_ploadrbtnew_abs: in isSignExtendingLoad()
2605 case Hexagon::L4_ploadrbfnew_abs: in isSignExtendingLoad()
2606 case Hexagon::L2_loadrbgp: in isSignExtendingLoad()
2608 case Hexagon::L2_loadrh_io: in isSignExtendingLoad()
2609 case Hexagon::L4_loadrh_ur: in isSignExtendingLoad()
2610 case Hexagon::L4_loadrh_ap: in isSignExtendingLoad()
2611 case Hexagon::L2_loadrh_pr: in isSignExtendingLoad()
2612 case Hexagon::L2_loadrh_pbr: in isSignExtendingLoad()
2613 case Hexagon::L2_loadrh_pi: in isSignExtendingLoad()
2614 case Hexagon::L2_loadrh_pci: in isSignExtendingLoad()
2615 case Hexagon::L2_loadrh_pcr: in isSignExtendingLoad()
2616 case Hexagon::L4_loadrh_rr: in isSignExtendingLoad()
2617 case Hexagon::L2_ploadrht_io: in isSignExtendingLoad()
2618 case Hexagon::L2_ploadrht_pi: in isSignExtendingLoad()
2619 case Hexagon::L2_ploadrhf_io: in isSignExtendingLoad()
2620 case Hexagon::L2_ploadrhf_pi: in isSignExtendingLoad()
2621 case Hexagon::L2_ploadrhtnew_io: in isSignExtendingLoad()
2622 case Hexagon::L2_ploadrhfnew_io: in isSignExtendingLoad()
2623 case Hexagon::L4_ploadrht_rr: in isSignExtendingLoad()
2624 case Hexagon::L4_ploadrhf_rr: in isSignExtendingLoad()
2625 case Hexagon::L4_ploadrhtnew_rr: in isSignExtendingLoad()
2626 case Hexagon::L4_ploadrhfnew_rr: in isSignExtendingLoad()
2627 case Hexagon::L2_ploadrhtnew_pi: in isSignExtendingLoad()
2628 case Hexagon::L2_ploadrhfnew_pi: in isSignExtendingLoad()
2629 case Hexagon::L4_ploadrht_abs: in isSignExtendingLoad()
2630 case Hexagon::L4_ploadrhf_abs: in isSignExtendingLoad()
2631 case Hexagon::L4_ploadrhtnew_abs: in isSignExtendingLoad()
2632 case Hexagon::L4_ploadrhfnew_abs: in isSignExtendingLoad()
2633 case Hexagon::L2_loadrhgp: in isSignExtendingLoad()
2647 case Hexagon::STriw_pred: in isSpillPredRegOp()
2648 case Hexagon::LDriw_pred: in isSpillPredRegOp()
2698 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2759 case Hexagon::PS_vstorerq_ai: in isValidOffset()
2760 case Hexagon::PS_vstorerv_ai: in isValidOffset()
2761 case Hexagon::PS_vstorerw_ai: in isValidOffset()
2762 case Hexagon::PS_vstorerw_nt_ai: in isValidOffset()
2763 case Hexagon::PS_vloadrq_ai: in isValidOffset()
2764 case Hexagon::PS_vloadrv_ai: in isValidOffset()
2765 case Hexagon::PS_vloadrw_ai: in isValidOffset()
2766 case Hexagon::PS_vloadrw_nt_ai: in isValidOffset()
2767 case Hexagon::V6_vL32b_ai: in isValidOffset()
2768 case Hexagon::V6_vS32b_ai: in isValidOffset()
2769 case Hexagon::V6_vS32b_pred_ai: in isValidOffset()
2770 case Hexagon::V6_vS32b_npred_ai: in isValidOffset()
2771 case Hexagon::V6_vS32b_qpred_ai: in isValidOffset()
2772 case Hexagon::V6_vS32b_nqpred_ai: in isValidOffset()
2773 case Hexagon::V6_vS32b_new_ai: in isValidOffset()
2774 case Hexagon::V6_vS32b_new_pred_ai: in isValidOffset()
2775 case Hexagon::V6_vS32b_new_npred_ai: in isValidOffset()
2776 case Hexagon::V6_vS32b_nt_pred_ai: in isValidOffset()
2777 case Hexagon::V6_vS32b_nt_npred_ai: in isValidOffset()
2778 case Hexagon::V6_vS32b_nt_new_ai: in isValidOffset()
2779 case Hexagon::V6_vS32b_nt_new_pred_ai: in isValidOffset()
2780 case Hexagon::V6_vS32b_nt_new_npred_ai: in isValidOffset()
2781 case Hexagon::V6_vS32b_nt_qpred_ai: in isValidOffset()
2782 case Hexagon::V6_vS32b_nt_nqpred_ai: in isValidOffset()
2783 case Hexagon::V6_vL32b_nt_ai: in isValidOffset()
2784 case Hexagon::V6_vS32b_nt_ai: in isValidOffset()
2785 case Hexagon::V6_vL32Ub_ai: in isValidOffset()
2786 case Hexagon::V6_vS32Ub_ai: in isValidOffset()
2787 case Hexagon::V6_vL32b_cur_ai: in isValidOffset()
2788 case Hexagon::V6_vL32b_tmp_ai: in isValidOffset()
2789 case Hexagon::V6_vL32b_pred_ai: in isValidOffset()
2790 case Hexagon::V6_vL32b_npred_ai: in isValidOffset()
2791 case Hexagon::V6_vL32b_cur_pred_ai: in isValidOffset()
2792 case Hexagon::V6_vL32b_cur_npred_ai: in isValidOffset()
2793 case Hexagon::V6_vL32b_tmp_pred_ai: in isValidOffset()
2794 case Hexagon::V6_vL32b_tmp_npred_ai: in isValidOffset()
2795 case Hexagon::V6_vL32b_nt_cur_ai: in isValidOffset()
2796 case Hexagon::V6_vL32b_nt_tmp_ai: in isValidOffset()
2797 case Hexagon::V6_vL32b_nt_pred_ai: in isValidOffset()
2798 case Hexagon::V6_vL32b_nt_npred_ai: in isValidOffset()
2799 case Hexagon::V6_vL32b_nt_cur_pred_ai: in isValidOffset()
2800 case Hexagon::V6_vL32b_nt_cur_npred_ai: in isValidOffset()
2801 case Hexagon::V6_vL32b_nt_tmp_pred_ai: in isValidOffset()
2802 case Hexagon::V6_vL32b_nt_tmp_npred_ai: in isValidOffset()
2803 case Hexagon::V6_vgathermh_pseudo: in isValidOffset()
2804 case Hexagon::V6_vgathermw_pseudo: in isValidOffset()
2805 case Hexagon::V6_vgathermhw_pseudo: in isValidOffset()
2806 case Hexagon::V6_vgathermhq_pseudo: in isValidOffset()
2807 case Hexagon::V6_vgathermwq_pseudo: in isValidOffset()
2808 case Hexagon::V6_vgathermhwq_pseudo: { in isValidOffset()
2809 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); in isValidOffset()
2816 case Hexagon::J2_loop0i: in isValidOffset()
2817 case Hexagon::J2_loop1i: in isValidOffset()
2820 case Hexagon::S4_storeirb_io: in isValidOffset()
2821 case Hexagon::S4_storeirbt_io: in isValidOffset()
2822 case Hexagon::S4_storeirbf_io: in isValidOffset()
2825 case Hexagon::S4_storeirh_io: in isValidOffset()
2826 case Hexagon::S4_storeirht_io: in isValidOffset()
2827 case Hexagon::S4_storeirhf_io: in isValidOffset()
2830 case Hexagon::S4_storeiri_io: in isValidOffset()
2831 case Hexagon::S4_storeirit_io: in isValidOffset()
2832 case Hexagon::S4_storeirif_io: in isValidOffset()
2835 case Hexagon::A4_cmpbeqi: in isValidOffset()
2837 case Hexagon::A4_cmpbgti: in isValidOffset()
2845 case Hexagon::L2_loadri_io: in isValidOffset()
2846 case Hexagon::S2_storeri_io: in isValidOffset()
2850 case Hexagon::L2_loadrd_io: in isValidOffset()
2851 case Hexagon::S2_storerd_io: in isValidOffset()
2855 case Hexagon::L2_loadrh_io: in isValidOffset()
2856 case Hexagon::L2_loadruh_io: in isValidOffset()
2857 case Hexagon::S2_storerh_io: in isValidOffset()
2858 case Hexagon::S2_storerf_io: in isValidOffset()
2862 case Hexagon::L2_loadrb_io: in isValidOffset()
2863 case Hexagon::L2_loadrub_io: in isValidOffset()
2864 case Hexagon::S2_storerb_io: in isValidOffset()
2868 case Hexagon::A2_addi: in isValidOffset()
2872 case Hexagon::L4_iadd_memopw_io: in isValidOffset()
2873 case Hexagon::L4_isub_memopw_io: in isValidOffset()
2874 case Hexagon::L4_add_memopw_io: in isValidOffset()
2875 case Hexagon::L4_sub_memopw_io: in isValidOffset()
2876 case Hexagon::L4_iand_memopw_io: in isValidOffset()
2877 case Hexagon::L4_ior_memopw_io: in isValidOffset()
2878 case Hexagon::L4_and_memopw_io: in isValidOffset()
2879 case Hexagon::L4_or_memopw_io: in isValidOffset()
2882 case Hexagon::L4_iadd_memoph_io: in isValidOffset()
2883 case Hexagon::L4_isub_memoph_io: in isValidOffset()
2884 case Hexagon::L4_add_memoph_io: in isValidOffset()
2885 case Hexagon::L4_sub_memoph_io: in isValidOffset()
2886 case Hexagon::L4_iand_memoph_io: in isValidOffset()
2887 case Hexagon::L4_ior_memoph_io: in isValidOffset()
2888 case Hexagon::L4_and_memoph_io: in isValidOffset()
2889 case Hexagon::L4_or_memoph_io: in isValidOffset()
2892 case Hexagon::L4_iadd_memopb_io: in isValidOffset()
2893 case Hexagon::L4_isub_memopb_io: in isValidOffset()
2894 case Hexagon::L4_add_memopb_io: in isValidOffset()
2895 case Hexagon::L4_sub_memopb_io: in isValidOffset()
2896 case Hexagon::L4_iand_memopb_io: in isValidOffset()
2897 case Hexagon::L4_ior_memopb_io: in isValidOffset()
2898 case Hexagon::L4_and_memopb_io: in isValidOffset()
2899 case Hexagon::L4_or_memopb_io: in isValidOffset()
2904 case Hexagon::STriw_pred: in isValidOffset()
2905 case Hexagon::LDriw_pred: in isValidOffset()
2906 case Hexagon::STriw_ctr: in isValidOffset()
2907 case Hexagon::LDriw_ctr: in isValidOffset()
2910 case Hexagon::PS_fi: in isValidOffset()
2911 case Hexagon::PS_fia: in isValidOffset()
2912 case Hexagon::INLINEASM: in isValidOffset()
2915 case Hexagon::L2_ploadrbt_io: in isValidOffset()
2916 case Hexagon::L2_ploadrbf_io: in isValidOffset()
2917 case Hexagon::L2_ploadrubt_io: in isValidOffset()
2918 case Hexagon::L2_ploadrubf_io: in isValidOffset()
2919 case Hexagon::S2_pstorerbt_io: in isValidOffset()
2920 case Hexagon::S2_pstorerbf_io: in isValidOffset()
2923 case Hexagon::L2_ploadrht_io: in isValidOffset()
2924 case Hexagon::L2_ploadrhf_io: in isValidOffset()
2925 case Hexagon::L2_ploadruht_io: in isValidOffset()
2926 case Hexagon::L2_ploadruhf_io: in isValidOffset()
2927 case Hexagon::S2_pstorerht_io: in isValidOffset()
2928 case Hexagon::S2_pstorerhf_io: in isValidOffset()
2931 case Hexagon::L2_ploadrit_io: in isValidOffset()
2932 case Hexagon::L2_ploadrif_io: in isValidOffset()
2933 case Hexagon::S2_pstorerit_io: in isValidOffset()
2934 case Hexagon::S2_pstorerif_io: in isValidOffset()
2937 case Hexagon::L2_ploadrdt_io: in isValidOffset()
2938 case Hexagon::L2_ploadrdf_io: in isValidOffset()
2939 case Hexagon::S2_pstorerdt_io: in isValidOffset()
2940 case Hexagon::S2_pstorerdf_io: in isValidOffset()
2943 case Hexagon::L2_loadbsw2_io: in isValidOffset()
2944 case Hexagon::L2_loadbzw2_io: in isValidOffset()
2947 case Hexagon::L2_loadbsw4_io: in isValidOffset()
2948 case Hexagon::L2_loadbzw4_io: in isValidOffset()
2987 case Hexagon::L2_loadrub_io: in isZeroExtendingLoad()
2988 case Hexagon::L4_loadrub_ur: in isZeroExtendingLoad()
2989 case Hexagon::L4_loadrub_ap: in isZeroExtendingLoad()
2990 case Hexagon::L2_loadrub_pr: in isZeroExtendingLoad()
2991 case Hexagon::L2_loadrub_pbr: in isZeroExtendingLoad()
2992 case Hexagon::L2_loadrub_pi: in isZeroExtendingLoad()
2993 case Hexagon::L2_loadrub_pci: in isZeroExtendingLoad()
2994 case Hexagon::L2_loadrub_pcr: in isZeroExtendingLoad()
2995 case Hexagon::L2_loadbzw2_io: in isZeroExtendingLoad()
2996 case Hexagon::L4_loadbzw2_ur: in isZeroExtendingLoad()
2997 case Hexagon::L4_loadbzw2_ap: in isZeroExtendingLoad()
2998 case Hexagon::L2_loadbzw2_pr: in isZeroExtendingLoad()
2999 case Hexagon::L2_loadbzw2_pbr: in isZeroExtendingLoad()
3000 case Hexagon::L2_loadbzw2_pi: in isZeroExtendingLoad()
3001 case Hexagon::L2_loadbzw2_pci: in isZeroExtendingLoad()
3002 case Hexagon::L2_loadbzw2_pcr: in isZeroExtendingLoad()
3003 case Hexagon::L2_loadbzw4_io: in isZeroExtendingLoad()
3004 case Hexagon::L4_loadbzw4_ur: in isZeroExtendingLoad()
3005 case Hexagon::L4_loadbzw4_ap: in isZeroExtendingLoad()
3006 case Hexagon::L2_loadbzw4_pr: in isZeroExtendingLoad()
3007 case Hexagon::L2_loadbzw4_pbr: in isZeroExtendingLoad()
3008 case Hexagon::L2_loadbzw4_pi: in isZeroExtendingLoad()
3009 case Hexagon::L2_loadbzw4_pci: in isZeroExtendingLoad()
3010 case Hexagon::L2_loadbzw4_pcr: in isZeroExtendingLoad()
3011 case Hexagon::L4_loadrub_rr: in isZeroExtendingLoad()
3012 case Hexagon::L2_ploadrubt_io: in isZeroExtendingLoad()
3013 case Hexagon::L2_ploadrubt_pi: in isZeroExtendingLoad()
3014 case Hexagon::L2_ploadrubf_io: in isZeroExtendingLoad()
3015 case Hexagon::L2_ploadrubf_pi: in isZeroExtendingLoad()
3016 case Hexagon::L2_ploadrubtnew_io: in isZeroExtendingLoad()
3017 case Hexagon::L2_ploadrubfnew_io: in isZeroExtendingLoad()
3018 case Hexagon::L4_ploadrubt_rr: in isZeroExtendingLoad()
3019 case Hexagon::L4_ploadrubf_rr: in isZeroExtendingLoad()
3020 case Hexagon::L4_ploadrubtnew_rr: in isZeroExtendingLoad()
3021 case Hexagon::L4_ploadrubfnew_rr: in isZeroExtendingLoad()
3022 case Hexagon::L2_ploadrubtnew_pi: in isZeroExtendingLoad()
3023 case Hexagon::L2_ploadrubfnew_pi: in isZeroExtendingLoad()
3024 case Hexagon::L4_ploadrubt_abs: in isZeroExtendingLoad()
3025 case Hexagon::L4_ploadrubf_abs: in isZeroExtendingLoad()
3026 case Hexagon::L4_ploadrubtnew_abs: in isZeroExtendingLoad()
3027 case Hexagon::L4_ploadrubfnew_abs: in isZeroExtendingLoad()
3028 case Hexagon::L2_loadrubgp: in isZeroExtendingLoad()
3030 case Hexagon::L2_loadruh_io: in isZeroExtendingLoad()
3031 case Hexagon::L4_loadruh_ur: in isZeroExtendingLoad()
3032 case Hexagon::L4_loadruh_ap: in isZeroExtendingLoad()
3033 case Hexagon::L2_loadruh_pr: in isZeroExtendingLoad()
3034 case Hexagon::L2_loadruh_pbr: in isZeroExtendingLoad()
3035 case Hexagon::L2_loadruh_pi: in isZeroExtendingLoad()
3036 case Hexagon::L2_loadruh_pci: in isZeroExtendingLoad()
3037 case Hexagon::L2_loadruh_pcr: in isZeroExtendingLoad()
3038 case Hexagon::L4_loadruh_rr: in isZeroExtendingLoad()
3039 case Hexagon::L2_ploadruht_io: in isZeroExtendingLoad()
3040 case Hexagon::L2_ploadruht_pi: in isZeroExtendingLoad()
3041 case Hexagon::L2_ploadruhf_io: in isZeroExtendingLoad()
3042 case Hexagon::L2_ploadruhf_pi: in isZeroExtendingLoad()
3043 case Hexagon::L2_ploadruhtnew_io: in isZeroExtendingLoad()
3044 case Hexagon::L2_ploadruhfnew_io: in isZeroExtendingLoad()
3045 case Hexagon::L4_ploadruht_rr: in isZeroExtendingLoad()
3046 case Hexagon::L4_ploadruhf_rr: in isZeroExtendingLoad()
3047 case Hexagon::L4_ploadruhtnew_rr: in isZeroExtendingLoad()
3048 case Hexagon::L4_ploadruhfnew_rr: in isZeroExtendingLoad()
3049 case Hexagon::L2_ploadruhtnew_pi: in isZeroExtendingLoad()
3050 case Hexagon::L2_ploadruhfnew_pi: in isZeroExtendingLoad()
3051 case Hexagon::L4_ploadruht_abs: in isZeroExtendingLoad()
3052 case Hexagon::L4_ploadruhf_abs: in isZeroExtendingLoad()
3053 case Hexagon::L4_ploadruhtnew_abs: in isZeroExtendingLoad()
3054 case Hexagon::L4_ploadruhfnew_abs: in isZeroExtendingLoad()
3055 case Hexagon::L2_loadruhgp: in isZeroExtendingLoad()
3087 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) { in canExecuteInBundle()
3089 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29) in canExecuteInBundle()
3112 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr; in doesNotReturn()
3128 if (Hexagon::getRegForm(MI.getOpcode()) >= 0) in hasNonExtEquivalent()
3138 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode()); in hasNonExtEquivalent()
3144 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode()); in hasNonExtEquivalent()
3147 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode()); in hasNonExtEquivalent()
3160 return Hexagon::getRealHWInstr(MI.getOpcode(), in hasPseudoInstrPair()
3161 Hexagon::InstrType_Pseudo) >= 0; in hasPseudoInstrPair()
3242 case Hexagon::A4_addp_c: in predCanBeUsedAsDotNew()
3243 case Hexagon::A4_subp_c: in predCanBeUsedAsDotNew()
3244 case Hexagon::A4_tlbmatch: in predCanBeUsedAsDotNew()
3245 case Hexagon::A5_ACS: in predCanBeUsedAsDotNew()
3246 case Hexagon::F2_sfinvsqrta: in predCanBeUsedAsDotNew()
3247 case Hexagon::F2_sfrecipa: in predCanBeUsedAsDotNew()
3248 case Hexagon::J2_endloop0: in predCanBeUsedAsDotNew()
3249 case Hexagon::J2_endloop01: in predCanBeUsedAsDotNew()
3250 case Hexagon::J2_ploop1si: in predCanBeUsedAsDotNew()
3251 case Hexagon::J2_ploop1sr: in predCanBeUsedAsDotNew()
3252 case Hexagon::J2_ploop2si: in predCanBeUsedAsDotNew()
3253 case Hexagon::J2_ploop2sr: in predCanBeUsedAsDotNew()
3254 case Hexagon::J2_ploop3si: in predCanBeUsedAsDotNew()
3255 case Hexagon::J2_ploop3sr: in predCanBeUsedAsDotNew()
3256 case Hexagon::S2_cabacdecbin: in predCanBeUsedAsDotNew()
3257 case Hexagon::S2_storew_locked: in predCanBeUsedAsDotNew()
3258 case Hexagon::S4_stored_locked: in predCanBeUsedAsDotNew()
3265 return Opcode == Hexagon::J2_jumpt || in PredOpcodeHasJMP_c()
3266 Opcode == Hexagon::J2_jumptpt || in PredOpcodeHasJMP_c()
3267 Opcode == Hexagon::J2_jumpf || in PredOpcodeHasJMP_c()
3268 Opcode == Hexagon::J2_jumpfpt || in PredOpcodeHasJMP_c()
3269 Opcode == Hexagon::J2_jumptnew || in PredOpcodeHasJMP_c()
3270 Opcode == Hexagon::J2_jumpfnew || in PredOpcodeHasJMP_c()
3271 Opcode == Hexagon::J2_jumptnewpt || in PredOpcodeHasJMP_c()
3272 Opcode == Hexagon::J2_jumpfnewpt; in PredOpcodeHasJMP_c()
3438 case Hexagon::C2_cmpeq: in getCompoundCandidateGroup()
3439 case Hexagon::C2_cmpgt: in getCompoundCandidateGroup()
3440 case Hexagon::C2_cmpgtu: in getCompoundCandidateGroup()
3444 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3445 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3449 case Hexagon::C2_cmpeqi: in getCompoundCandidateGroup()
3450 case Hexagon::C2_cmpgti: in getCompoundCandidateGroup()
3451 case Hexagon::C2_cmpgtui: in getCompoundCandidateGroup()
3455 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3456 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3462 case Hexagon::A2_tfr: in getCompoundCandidateGroup()
3469 case Hexagon::A2_tfrsi: in getCompoundCandidateGroup()
3477 case Hexagon::S2_tstbit_i: in getCompoundCandidateGroup()
3480 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3481 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3490 case Hexagon::J2_jumptnew: in getCompoundCandidateGroup()
3491 case Hexagon::J2_jumpfnew: in getCompoundCandidateGroup()
3492 case Hexagon::J2_jumptnewpt: in getCompoundCandidateGroup()
3493 case Hexagon::J2_jumpfnewpt: in getCompoundCandidateGroup()
3495 if (Hexagon::PredRegsRegClass.contains(Src1Reg) && in getCompoundCandidateGroup()
3496 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)) in getCompoundCandidateGroup()
3503 case Hexagon::J2_jump: in getCompoundCandidateGroup()
3504 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in getCompoundCandidateGroup()
3505 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: in getCompoundCandidateGroup()
3517 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) || in getCompoundOpcode()
3518 (GB.getOpcode() != Hexagon::J2_jumptnew)) in getCompoundOpcode()
3523 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1) in getCompoundOpcode()
3531 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt in getCompoundOpcode()
3532 : Hexagon::J4_cmpeqn1_tp1_jump_nt; in getCompoundOpcode()
3535 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt in getCompoundOpcode()
3536 : Hexagon::J4_cmpeqi_tp1_jump_nt; in getCompoundOpcode()
3550 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3551 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3552 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3553 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii}, in getDuplexOpcode()
3554 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3555 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3556 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3557 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi}, in getDuplexOpcode()
3558 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
3559 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth}, in getDuplexOpcode()
3560 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii}, in getDuplexOpcode()
3561 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir}, in getDuplexOpcode()
3562 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri}, in getDuplexOpcode()
3563 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif}, in getDuplexOpcode()
3564 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit}, in getDuplexOpcode()
3565 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif}, in getDuplexOpcode()
3566 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit}, in getDuplexOpcode()
3567 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi}, in getDuplexOpcode()
3568 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe}, in getDuplexOpcode()
3569 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io}, in getDuplexOpcode()
3570 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io}, in getDuplexOpcode()
3571 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io}, in getDuplexOpcode()
3572 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io}, in getDuplexOpcode()
3573 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io}, in getDuplexOpcode()
3574 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io}, in getDuplexOpcode()
3575 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe}, in getDuplexOpcode()
3576 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io}, in getDuplexOpcode()
3577 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io}, in getDuplexOpcode()
3578 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io}, in getDuplexOpcode()
3579 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io}, in getDuplexOpcode()
3580 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io}, in getDuplexOpcode()
3581 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io}, in getDuplexOpcode()
3598 enum Hexagon::PredSense inPredSense; in getCondOpcode()
3599 inPredSense = invertPredicate ? Hexagon::PredSense_false : in getCondOpcode()
3600 Hexagon::PredSense_true; in getCondOpcode()
3601 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); in getCondOpcode()
3612 case Hexagon::V6_vL32b_pi: in getDotCurOp()
3613 return Hexagon::V6_vL32b_cur_pi; in getDotCurOp()
3614 case Hexagon::V6_vL32b_ai: in getDotCurOp()
3615 return Hexagon::V6_vL32b_cur_ai; in getDotCurOp()
3616 case Hexagon::V6_vL32b_nt_pi: in getDotCurOp()
3617 return Hexagon::V6_vL32b_nt_cur_pi; in getDotCurOp()
3618 case Hexagon::V6_vL32b_nt_ai: in getDotCurOp()
3619 return Hexagon::V6_vL32b_nt_cur_ai; in getDotCurOp()
3620 case Hexagon::V6_vL32b_ppu: in getDotCurOp()
3621 return Hexagon::V6_vL32b_cur_ppu; in getDotCurOp()
3622 case Hexagon::V6_vL32b_nt_ppu: in getDotCurOp()
3623 return Hexagon::V6_vL32b_nt_cur_ppu; in getDotCurOp()
3632 case Hexagon::V6_vL32b_cur_pi: in getNonDotCurOp()
3633 return Hexagon::V6_vL32b_pi; in getNonDotCurOp()
3634 case Hexagon::V6_vL32b_cur_ai: in getNonDotCurOp()
3635 return Hexagon::V6_vL32b_ai; in getNonDotCurOp()
3636 case Hexagon::V6_vL32b_nt_cur_pi: in getNonDotCurOp()
3637 return Hexagon::V6_vL32b_nt_pi; in getNonDotCurOp()
3638 case Hexagon::V6_vL32b_nt_cur_ai: in getNonDotCurOp()
3639 return Hexagon::V6_vL32b_nt_ai; in getNonDotCurOp()
3640 case Hexagon::V6_vL32b_cur_ppu: in getNonDotCurOp()
3641 return Hexagon::V6_vL32b_ppu; in getNonDotCurOp()
3642 case Hexagon::V6_vL32b_nt_cur_ppu: in getNonDotCurOp()
3643 return Hexagon::V6_vL32b_nt_ppu; in getNonDotCurOp()
3731 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode()); in getDotNewOp()
3739 case Hexagon::S4_storerb_ur: in getDotNewOp()
3740 return Hexagon::S4_storerbnew_ur; in getDotNewOp()
3742 case Hexagon::S2_storerb_pci: in getDotNewOp()
3743 return Hexagon::S2_storerb_pci; in getDotNewOp()
3745 case Hexagon::S2_storeri_pci: in getDotNewOp()
3746 return Hexagon::S2_storeri_pci; in getDotNewOp()
3748 case Hexagon::S2_storerh_pci: in getDotNewOp()
3749 return Hexagon::S2_storerh_pci; in getDotNewOp()
3751 case Hexagon::S2_storerd_pci: in getDotNewOp()
3752 return Hexagon::S2_storerd_pci; in getDotNewOp()
3754 case Hexagon::S2_storerf_pci: in getDotNewOp()
3755 return Hexagon::S2_storerf_pci; in getDotNewOp()
3757 case Hexagon::V6_vS32b_ai: in getDotNewOp()
3758 return Hexagon::V6_vS32b_new_ai; in getDotNewOp()
3760 case Hexagon::V6_vS32b_pi: in getDotNewOp()
3761 return Hexagon::V6_vS32b_new_pi; in getDotNewOp()
3846 case Hexagon::J2_jumpt: in getDotNewPredJumpOp()
3847 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew; in getDotNewPredJumpOp()
3848 case Hexagon::J2_jumpf: in getDotNewPredJumpOp()
3849 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew; in getDotNewPredJumpOp()
3861 case Hexagon::J2_jumpt: in getDotNewPredOp()
3862 case Hexagon::J2_jumpf: in getDotNewPredOp()
3866 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); in getDotNewPredOp()
3875 NewOp = Hexagon::getPredOldOpcode(NewOp); in getDotOldOp()
3879 if (!Subtarget.hasFeature(Hexagon::ArchV60)) { in getDotOldOp()
3881 case Hexagon::J2_jumptpt: in getDotOldOp()
3882 NewOp = Hexagon::J2_jumpt; in getDotOldOp()
3884 case Hexagon::J2_jumpfpt: in getDotOldOp()
3885 NewOp = Hexagon::J2_jumpf; in getDotOldOp()
3887 case Hexagon::J2_jumprtpt: in getDotOldOp()
3888 NewOp = Hexagon::J2_jumprt; in getDotOldOp()
3890 case Hexagon::J2_jumprfpt: in getDotOldOp()
3891 NewOp = Hexagon::J2_jumprf; in getDotOldOp()
3900 NewOp = Hexagon::getNonNVStore(NewOp); in getDotOldOp()
3909 case Hexagon::J2_jumpfpt: in getDotOldOp()
3910 return Hexagon::J2_jumpf; in getDotOldOp()
3911 case Hexagon::J2_jumptpt: in getDotOldOp()
3912 return Hexagon::J2_jumpt; in getDotOldOp()
3913 case Hexagon::J2_jumprfpt: in getDotOldOp()
3914 return Hexagon::J2_jumprf; in getDotOldOp()
3915 case Hexagon::J2_jumprtpt: in getDotOldOp()
3916 return Hexagon::J2_jumprt; in getDotOldOp()
3936 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
3937 case Hexagon::dup_L2_loadri_io: in getDuplexCandidateGroup()
3943 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3955 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
3956 case Hexagon::dup_L2_loadrub_io: in getDuplexCandidateGroup()
3974 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
3975 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
3976 case Hexagon::dup_L2_loadrh_io: in getDuplexCandidateGroup()
3977 case Hexagon::dup_L2_loadruh_io: in getDuplexCandidateGroup()
3986 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
3987 case Hexagon::dup_L2_loadrb_io: in getDuplexCandidateGroup()
3996 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
3997 case Hexagon::dup_L2_loadrd_io: in getDuplexCandidateGroup()
4002 Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4010 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in getDuplexCandidateGroup()
4011 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: in getDuplexCandidateGroup()
4012 case Hexagon::L4_return: in getDuplexCandidateGroup()
4013 case Hexagon::L2_deallocframe: in getDuplexCandidateGroup()
4014 case Hexagon::dup_L2_deallocframe: in getDuplexCandidateGroup()
4016 case Hexagon::EH_RETURN_JMPR: in getDuplexCandidateGroup()
4017 case Hexagon::PS_jmpret: in getDuplexCandidateGroup()
4018 case Hexagon::SL2_jumpr31: in getDuplexCandidateGroup()
4022 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)) in getDuplexCandidateGroup()
4025 case Hexagon::PS_jmprett: in getDuplexCandidateGroup()
4026 case Hexagon::PS_jmpretf: in getDuplexCandidateGroup()
4027 case Hexagon::PS_jmprettnewpt: in getDuplexCandidateGroup()
4028 case Hexagon::PS_jmpretfnewpt: in getDuplexCandidateGroup()
4029 case Hexagon::PS_jmprettnew: in getDuplexCandidateGroup()
4030 case Hexagon::PS_jmpretfnew: in getDuplexCandidateGroup()
4031 case Hexagon::SL2_jumpr31_t: in getDuplexCandidateGroup()
4032 case Hexagon::SL2_jumpr31_f: in getDuplexCandidateGroup()
4033 case Hexagon::SL2_jumpr31_tnew: in getDuplexCandidateGroup()
4034 case Hexagon::SL2_jumpr31_fnew: in getDuplexCandidateGroup()
4038 if ((Hexagon::PredRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4039 (Hexagon::P0 == SrcReg)) && in getDuplexCandidateGroup()
4040 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))) in getDuplexCandidateGroup()
4043 case Hexagon::L4_return_t: in getDuplexCandidateGroup()
4044 case Hexagon::L4_return_f: in getDuplexCandidateGroup()
4045 case Hexagon::L4_return_tnew_pnt: in getDuplexCandidateGroup()
4046 case Hexagon::L4_return_fnew_pnt: in getDuplexCandidateGroup()
4047 case Hexagon::L4_return_tnew_pt: in getDuplexCandidateGroup()
4048 case Hexagon::L4_return_fnew_pt: in getDuplexCandidateGroup()
4051 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg)) in getDuplexCandidateGroup()
4059 case Hexagon::S2_storeri_io: in getDuplexCandidateGroup()
4060 case Hexagon::dup_S2_storeri_io: in getDuplexCandidateGroup()
4065 if (Hexagon::IntRegsRegClass.contains(Src1Reg) && in getDuplexCandidateGroup()
4076 case Hexagon::S2_storerb_io: in getDuplexCandidateGroup()
4077 case Hexagon::dup_S2_storerb_io: in getDuplexCandidateGroup()
4094 case Hexagon::S2_storerh_io: in getDuplexCandidateGroup()
4095 case Hexagon::dup_S2_storerh_io: in getDuplexCandidateGroup()
4104 case Hexagon::S2_storerd_io: in getDuplexCandidateGroup()
4105 case Hexagon::dup_S2_storerd_io: in getDuplexCandidateGroup()
4110 Hexagon::IntRegsRegClass.contains(Src1Reg) && in getDuplexCandidateGroup()
4115 case Hexagon::S4_storeiri_io: in getDuplexCandidateGroup()
4116 case Hexagon::dup_S4_storeiri_io: in getDuplexCandidateGroup()
4124 case Hexagon::S4_storeirb_io: in getDuplexCandidateGroup()
4125 case Hexagon::dup_S4_storeirb_io: in getDuplexCandidateGroup()
4133 case Hexagon::S2_allocframe: in getDuplexCandidateGroup()
4134 case Hexagon::dup_S2_allocframe: in getDuplexCandidateGroup()
4157 case Hexagon::A2_addi: in getDuplexCandidateGroup()
4158 case Hexagon::dup_A2_addi: in getDuplexCandidateGroup()
4163 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4179 case Hexagon::A2_add: in getDuplexCandidateGroup()
4180 case Hexagon::dup_A2_add: in getDuplexCandidateGroup()
4189 case Hexagon::A2_andir: in getDuplexCandidateGroup()
4190 case Hexagon::dup_A2_andir: in getDuplexCandidateGroup()
4202 case Hexagon::A2_tfr: in getDuplexCandidateGroup()
4203 case Hexagon::dup_A2_tfr: in getDuplexCandidateGroup()
4210 case Hexagon::A2_tfrsi: in getDuplexCandidateGroup()
4211 case Hexagon::dup_A2_tfrsi: in getDuplexCandidateGroup()
4220 case Hexagon::C2_cmoveit: in getDuplexCandidateGroup()
4221 case Hexagon::C2_cmovenewit: in getDuplexCandidateGroup()
4222 case Hexagon::C2_cmoveif: in getDuplexCandidateGroup()
4223 case Hexagon::C2_cmovenewif: in getDuplexCandidateGroup()
4224 case Hexagon::dup_C2_cmoveit: in getDuplexCandidateGroup()
4225 case Hexagon::dup_C2_cmovenewit: in getDuplexCandidateGroup()
4226 case Hexagon::dup_C2_cmoveif: in getDuplexCandidateGroup()
4227 case Hexagon::dup_C2_cmovenewif: in getDuplexCandidateGroup()
4234 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg && in getDuplexCandidateGroup()
4238 case Hexagon::C2_cmpeqi: in getDuplexCandidateGroup()
4239 case Hexagon::dup_C2_cmpeqi: in getDuplexCandidateGroup()
4243 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getDuplexCandidateGroup()
4244 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4248 case Hexagon::A2_combineii: in getDuplexCandidateGroup()
4249 case Hexagon::A4_combineii: in getDuplexCandidateGroup()
4250 case Hexagon::dup_A2_combineii: in getDuplexCandidateGroup()
4251 case Hexagon::dup_A4_combineii: in getDuplexCandidateGroup()
4263 case Hexagon::A4_combineri: in getDuplexCandidateGroup()
4264 case Hexagon::dup_A4_combineri: in getDuplexCandidateGroup()
4274 case Hexagon::A4_combineir: in getDuplexCandidateGroup()
4275 case Hexagon::dup_A4_combineir: in getDuplexCandidateGroup()
4284 case Hexagon::A2_sxtb: in getDuplexCandidateGroup()
4285 case Hexagon::A2_sxth: in getDuplexCandidateGroup()
4286 case Hexagon::A2_zxtb: in getDuplexCandidateGroup()
4287 case Hexagon::A2_zxth: in getDuplexCandidateGroup()
4288 case Hexagon::dup_A2_sxtb: in getDuplexCandidateGroup()
4289 case Hexagon::dup_A2_sxth: in getDuplexCandidateGroup()
4290 case Hexagon::dup_A2_zxtb: in getDuplexCandidateGroup()
4291 case Hexagon::dup_A2_zxth: in getDuplexCandidateGroup()
4304 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real); in getEquivalentHWInstr()
4382 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc) in getInvertedPredicatedOpcode()
4383 : Hexagon::getTruePredOpcode(Opc); in getInvertedPredicatedOpcode()
4407 case Hexagon::L2_loadrbgp: in isAddrModeWithOffset()
4408 case Hexagon::L2_loadrdgp: in isAddrModeWithOffset()
4409 case Hexagon::L2_loadrhgp: in isAddrModeWithOffset()
4410 case Hexagon::L2_loadrigp: in isAddrModeWithOffset()
4411 case Hexagon::L2_loadrubgp: in isAddrModeWithOffset()
4412 case Hexagon::L2_loadruhgp: in isAddrModeWithOffset()
4413 case Hexagon::S2_storerbgp: in isAddrModeWithOffset()
4414 case Hexagon::S2_storerbnewgp: in isAddrModeWithOffset()
4415 case Hexagon::S2_storerhgp: in isAddrModeWithOffset()
4416 case Hexagon::S2_storerhnewgp: in isAddrModeWithOffset()
4417 case Hexagon::S2_storerigp: in isAddrModeWithOffset()
4418 case Hexagon::S2_storerinewgp: in isAddrModeWithOffset()
4419 case Hexagon::S2_storerdgp: in isAddrModeWithOffset()
4420 case Hexagon::S2_storerfgp: in isAddrModeWithOffset()
4438 if (MI.getOpcode() == Hexagon::A4_ext) in isPureSlot0()
4497 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo) in getMemAccessSize()
4504 return HRI.getSpillSize(Hexagon::HvxVRRegClass); in getMemAccessSize()
4528 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode()); in getNonExtOpcode()
4536 return Hexagon::changeAddrMode_abs_io(MI.getOpcode()); in getNonExtOpcode()
4538 return Hexagon::changeAddrMode_io_rr(MI.getOpcode()); in getNonExtOpcode()
4540 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode()); in getNonExtOpcode()
4570 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo); in getPseudoInstrPair()
4574 return Hexagon::getRegForm(MI.getOpcode()); in getRegForm()
4595 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) { in getSize()
4685 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) { in genAllInsnTimingClasses()
4708 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode); in reversePrediction()
4710 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode); in reversePrediction()
4739 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc; in changeAddrMode_abs_io()
4743 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc; in changeAddrMode_io_abs()
4747 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc; in changeAddrMode_io_pi()
4751 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc; in changeAddrMode_io_rr()
4755 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc; in changeAddrMode_pi_io()
4759 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc; in changeAddrMode_rr_io()
4763 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc; in changeAddrMode_rr_ur()
4767 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc; in changeAddrMode_ur_rr()
4771 static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop); in getNop()
4773 return MCInstBuilder(Hexagon::BUNDLE) in getNop()