Lines Matching refs:Hexagon
70 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
72 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
136 if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) in PrintAsmOperand()
138 Hexagon::isub_lo : in PrintAsmOperand()
139 Hexagon::isub_hi); in PrintAsmOperand()
272 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
278 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
279 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
286 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
291 case Hexagon::A2_tfrf: { in HexagonProcessInstruction()
293 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
298 case Hexagon::A2_tfrt: { in HexagonProcessInstruction()
300 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
305 case Hexagon::A2_tfrfnew: { in HexagonProcessInstruction()
307 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction()
312 case Hexagon::A2_tfrtnew: { in HexagonProcessInstruction()
314 Inst.setOpcode(Hexagon::A2_padditnew); in HexagonProcessInstruction()
319 case Hexagon::A2_zxtb: { in HexagonProcessInstruction()
321 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
327 case Hexagon::CONST64: in HexagonProcessInstruction()
338 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
346 case Hexagon::CONST32: in HexagonProcessInstruction()
355 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
366 case Hexagon::C2_pxfer_map: { in HexagonProcessInstruction()
368 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
376 case Hexagon::M2_vrcmpys_acc_s1: { in HexagonProcessInstruction()
381 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); in HexagonProcessInstruction()
383 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); in HexagonProcessInstruction()
387 case Hexagon::M2_vrcmpys_s1: { in HexagonProcessInstruction()
392 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h); in HexagonProcessInstruction()
394 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l); in HexagonProcessInstruction()
399 case Hexagon::M2_vrcmpys_s1rp: { in HexagonProcessInstruction()
404 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); in HexagonProcessInstruction()
406 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); in HexagonProcessInstruction()
411 case Hexagon::A4_boundscheck: { in HexagonProcessInstruction()
416 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi); in HexagonProcessInstruction()
418 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo); in HexagonProcessInstruction()
423 case Hexagon::PS_call_nr: in HexagonProcessInstruction()
424 Inst.setOpcode(Hexagon::J2_call); in HexagonProcessInstruction()
427 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { in HexagonProcessInstruction()
436 TmpInst.setOpcode(Hexagon::S2_vsathub); in HexagonProcessInstruction()
442 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat); in HexagonProcessInstruction()
453 case Hexagon::S5_vasrhrnd_goodsyntax: in HexagonProcessInstruction()
454 case Hexagon::S2_asr_i_p_rnd_goodsyntax: { in HexagonProcessInstruction()
463 TmpInst.setOpcode(Hexagon::A2_combinew); in HexagonProcessInstruction()
466 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
467 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
475 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax) in HexagonProcessInstruction()
476 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd); in HexagonProcessInstruction()
478 TmpInst.setOpcode(Hexagon::S5_vasrhrnd); in HexagonProcessInstruction()
490 case Hexagon::S2_asr_i_r_rnd_goodsyntax: { in HexagonProcessInstruction()
499 TmpInst.setOpcode(Hexagon::A2_tfr); in HexagonProcessInstruction()
505 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd); in HexagonProcessInstruction()
517 case Hexagon::A2_tfrpi: { in HexagonProcessInstruction()
522 TmpInst.setOpcode(Hexagon::A2_combineii); in HexagonProcessInstruction()
541 case Hexagon::A2_tfrp: { in HexagonProcessInstruction()
543 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
544 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
548 MappedInst.setOpcode(Hexagon::A2_combinew); in HexagonProcessInstruction()
552 case Hexagon::A2_tfrpt: in HexagonProcessInstruction()
553 case Hexagon::A2_tfrpf: { in HexagonProcessInstruction()
555 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
556 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
560 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in HexagonProcessInstruction()
561 ? Hexagon::C2_ccombinewt in HexagonProcessInstruction()
562 : Hexagon::C2_ccombinewf); in HexagonProcessInstruction()
566 case Hexagon::A2_tfrptnew: in HexagonProcessInstruction()
567 case Hexagon::A2_tfrpfnew: { in HexagonProcessInstruction()
569 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
570 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
574 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew in HexagonProcessInstruction()
575 ? Hexagon::C2_ccombinewnewt in HexagonProcessInstruction()
576 : Hexagon::C2_ccombinewnewf); in HexagonProcessInstruction()
580 case Hexagon::M2_mpysmi: { in HexagonProcessInstruction()
588 MappedInst.setOpcode(Hexagon::M2_mpysin); in HexagonProcessInstruction()
592 MappedInst.setOpcode(Hexagon::M2_mpysip); in HexagonProcessInstruction()
596 case Hexagon::A2_addsp: { in HexagonProcessInstruction()
601 MappedInst.setOpcode(Hexagon::A2_addsph); in HexagonProcessInstruction()
603 MappedInst.setOpcode(Hexagon::A2_addspl); in HexagonProcessInstruction()
608 case Hexagon::V6_vd0: { in HexagonProcessInstruction()
613 TmpInst.setOpcode(Hexagon::V6_vxor); in HexagonProcessInstruction()
621 case Hexagon::V6_vdd0: { in HexagonProcessInstruction()
626 TmpInst.setOpcode(Hexagon::V6_vsubw_dv); in HexagonProcessInstruction()
634 case Hexagon::V6_vL32Ub_pi: in HexagonProcessInstruction()
635 case Hexagon::V6_vL32b_cur_pi: in HexagonProcessInstruction()
636 case Hexagon::V6_vL32b_nt_cur_pi: in HexagonProcessInstruction()
637 case Hexagon::V6_vL32b_pi: in HexagonProcessInstruction()
638 case Hexagon::V6_vL32b_nt_pi: in HexagonProcessInstruction()
639 case Hexagon::V6_vL32b_nt_tmp_pi: in HexagonProcessInstruction()
640 case Hexagon::V6_vL32b_tmp_pi: in HexagonProcessInstruction()
644 case Hexagon::V6_vL32Ub_ai: in HexagonProcessInstruction()
645 case Hexagon::V6_vL32b_ai: in HexagonProcessInstruction()
646 case Hexagon::V6_vL32b_cur_ai: in HexagonProcessInstruction()
647 case Hexagon::V6_vL32b_nt_ai: in HexagonProcessInstruction()
648 case Hexagon::V6_vL32b_nt_cur_ai: in HexagonProcessInstruction()
649 case Hexagon::V6_vL32b_nt_tmp_ai: in HexagonProcessInstruction()
650 case Hexagon::V6_vL32b_tmp_ai: in HexagonProcessInstruction()
654 case Hexagon::V6_vS32Ub_pi: in HexagonProcessInstruction()
655 case Hexagon::V6_vS32b_new_pi: in HexagonProcessInstruction()
656 case Hexagon::V6_vS32b_nt_new_pi: in HexagonProcessInstruction()
657 case Hexagon::V6_vS32b_nt_pi: in HexagonProcessInstruction()
658 case Hexagon::V6_vS32b_pi: in HexagonProcessInstruction()
662 case Hexagon::V6_vS32Ub_ai: in HexagonProcessInstruction()
663 case Hexagon::V6_vS32b_ai: in HexagonProcessInstruction()
664 case Hexagon::V6_vS32b_new_ai: in HexagonProcessInstruction()
665 case Hexagon::V6_vS32b_nt_ai: in HexagonProcessInstruction()
666 case Hexagon::V6_vS32b_nt_new_ai: in HexagonProcessInstruction()
670 case Hexagon::V6_vL32b_cur_npred_pi: in HexagonProcessInstruction()
671 case Hexagon::V6_vL32b_cur_pred_pi: in HexagonProcessInstruction()
672 case Hexagon::V6_vL32b_npred_pi: in HexagonProcessInstruction()
673 case Hexagon::V6_vL32b_nt_cur_npred_pi: in HexagonProcessInstruction()
674 case Hexagon::V6_vL32b_nt_cur_pred_pi: in HexagonProcessInstruction()
675 case Hexagon::V6_vL32b_nt_npred_pi: in HexagonProcessInstruction()
676 case Hexagon::V6_vL32b_nt_pred_pi: in HexagonProcessInstruction()
677 case Hexagon::V6_vL32b_nt_tmp_npred_pi: in HexagonProcessInstruction()
678 case Hexagon::V6_vL32b_nt_tmp_pred_pi: in HexagonProcessInstruction()
679 case Hexagon::V6_vL32b_pred_pi: in HexagonProcessInstruction()
680 case Hexagon::V6_vL32b_tmp_npred_pi: in HexagonProcessInstruction()
681 case Hexagon::V6_vL32b_tmp_pred_pi: in HexagonProcessInstruction()
685 case Hexagon::V6_vL32b_cur_npred_ai: in HexagonProcessInstruction()
686 case Hexagon::V6_vL32b_cur_pred_ai: in HexagonProcessInstruction()
687 case Hexagon::V6_vL32b_npred_ai: in HexagonProcessInstruction()
688 case Hexagon::V6_vL32b_nt_cur_npred_ai: in HexagonProcessInstruction()
689 case Hexagon::V6_vL32b_nt_cur_pred_ai: in HexagonProcessInstruction()
690 case Hexagon::V6_vL32b_nt_npred_ai: in HexagonProcessInstruction()
691 case Hexagon::V6_vL32b_nt_pred_ai: in HexagonProcessInstruction()
692 case Hexagon::V6_vL32b_nt_tmp_npred_ai: in HexagonProcessInstruction()
693 case Hexagon::V6_vL32b_nt_tmp_pred_ai: in HexagonProcessInstruction()
694 case Hexagon::V6_vL32b_pred_ai: in HexagonProcessInstruction()
695 case Hexagon::V6_vL32b_tmp_npred_ai: in HexagonProcessInstruction()
696 case Hexagon::V6_vL32b_tmp_pred_ai: in HexagonProcessInstruction()
700 case Hexagon::V6_vS32Ub_npred_pi: in HexagonProcessInstruction()
701 case Hexagon::V6_vS32Ub_pred_pi: in HexagonProcessInstruction()
702 case Hexagon::V6_vS32b_new_npred_pi: in HexagonProcessInstruction()
703 case Hexagon::V6_vS32b_new_pred_pi: in HexagonProcessInstruction()
704 case Hexagon::V6_vS32b_npred_pi: in HexagonProcessInstruction()
705 case Hexagon::V6_vS32b_nqpred_pi: in HexagonProcessInstruction()
706 case Hexagon::V6_vS32b_nt_new_npred_pi: in HexagonProcessInstruction()
707 case Hexagon::V6_vS32b_nt_new_pred_pi: in HexagonProcessInstruction()
708 case Hexagon::V6_vS32b_nt_npred_pi: in HexagonProcessInstruction()
709 case Hexagon::V6_vS32b_nt_nqpred_pi: in HexagonProcessInstruction()
710 case Hexagon::V6_vS32b_nt_pred_pi: in HexagonProcessInstruction()
711 case Hexagon::V6_vS32b_nt_qpred_pi: in HexagonProcessInstruction()
712 case Hexagon::V6_vS32b_pred_pi: in HexagonProcessInstruction()
713 case Hexagon::V6_vS32b_qpred_pi: in HexagonProcessInstruction()
717 case Hexagon::V6_vS32Ub_npred_ai: in HexagonProcessInstruction()
718 case Hexagon::V6_vS32Ub_pred_ai: in HexagonProcessInstruction()
719 case Hexagon::V6_vS32b_new_npred_ai: in HexagonProcessInstruction()
720 case Hexagon::V6_vS32b_new_pred_ai: in HexagonProcessInstruction()
721 case Hexagon::V6_vS32b_npred_ai: in HexagonProcessInstruction()
722 case Hexagon::V6_vS32b_nqpred_ai: in HexagonProcessInstruction()
723 case Hexagon::V6_vS32b_nt_new_npred_ai: in HexagonProcessInstruction()
724 case Hexagon::V6_vS32b_nt_new_pred_ai: in HexagonProcessInstruction()
725 case Hexagon::V6_vS32b_nt_npred_ai: in HexagonProcessInstruction()
726 case Hexagon::V6_vS32b_nt_nqpred_ai: in HexagonProcessInstruction()
727 case Hexagon::V6_vS32b_nt_pred_ai: in HexagonProcessInstruction()
728 case Hexagon::V6_vS32b_nt_qpred_ai: in HexagonProcessInstruction()
729 case Hexagon::V6_vS32b_pred_ai: in HexagonProcessInstruction()
730 case Hexagon::V6_vS32b_qpred_ai: in HexagonProcessInstruction()
735 case Hexagon::V6_vS32b_srls_ai: in HexagonProcessInstruction()
739 case Hexagon::V6_vS32b_srls_pi: in HexagonProcessInstruction()
751 MCB.setOpcode(Hexagon::BUNDLE); in emitInstruction()
826 SledJump->setOpcode(Hexagon::J2_jump); in EmitSled()
833 SledJumpPacket.setOpcode(Hexagon::BUNDLE); in EmitSled()