| /freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/ |
| H A D | DXIL.td | 40 def HalfTy : DXILOpParamType;
409 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
420 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy]>];
429 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
439 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
448 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
457 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
467 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
477 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
487 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy]>];
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| H A D | DXILOpBuilder.cpp | 269 case OpParamType::HalfTy: in getTypeFromOpParamType()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | ARM.cpp | 380 return llvm::FixedVectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad)); in GetNeonType()
406 return llvm::FixedVectorType::get(CGF->HalfTy, (4 << IsQuad)); in GetFloatNeonType()
1847 Ty = HalfTy; in EmitCommonNeonBuiltinExpr()
2369 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
2376 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
2383 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
2390 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
5795 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::fabs, HalfTy), Ops, "vabs"); in EmitAArch64BuiltinExpr()
5839 llvm::Type *FTy = HalfTy; in EmitAArch64BuiltinExpr()
5864 llvm::Type* FTy = HalfTy; in EmitAArch64BuiltinExpr()
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| H A D | X86.cpp | 601 auto *HalfTy = llvm::FixedVectorType::get( in EmitX86CvtF16ToFloatExpr() local
603 Src = CGF.Builder.CreateBitCast(Src, HalfTy); in EmitX86CvtF16ToFloatExpr()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenTypeCache.h | 39 llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 479 MVT HalfTy = typeSplit(Ty).first; in LoHalf() local
481 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in LoHalf()
490 MVT HalfTy = typeSplit(Ty).first; in HiHalf() local
491 SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32); in HiHalf()
492 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in HiHalf()
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| H A D | HexagonISelLoweringHVX.cpp | 530 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2); in typeSplit() local
531 return { HalfTy, HalfTy }; in typeSplit()
1746 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxConcatVectors() local
1747 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1749 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
2295 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxFpExtend() local
2298 getInstr(Hexagon::V6_vconv_sf_qf32, dl, HalfTy, {Pair.first}, DAG); in LowerHvxFpExtend()
2300 getInstr(Hexagon::V6_vconv_sf_qf32, dl, HalfTy, {Pair.second}, DAG); in LowerHvxFpExtend()
2995 MVT HalfTy = typeSplit(ResTy).first; in SplitVectorOp() local
2996 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL); in SplitVectorOp()
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| H A D | HexagonISelDAGToDAGHVX.cpp | 1186 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), in materialize() local
1190 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1510 MVT HalfTy = getSingleVT(MVT::i8); in packp() local
1513 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) }; in packp()
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| H A D | HexagonISelLowering.cpp | 2683 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2); in buildVector64() local
2686 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG); in buildVector64()
2689 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG); in buildVector64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 662 LLT HalfTy, in split64BitValueForMapping() argument
664 assert(HalfTy.getSizeInBits() == 32); in split64BitValueForMapping()
666 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
667 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
2157 LLT HalfTy = LLT::scalar(32); in applyMappingSMULU64() local
2164 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg()); in applyMappingSMULU64()
2166 setRegsToType(MRI, Src0Regs, HalfTy); in applyMappingSMULU64()
2169 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); in applyMappingSMULU64()
2171 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingSMULU64()
2173 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingSMULU64()
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| H A D | AMDGPURegisterBankInfo.h | 128 LLT HalfTy,
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 835 Type *HalfTy = Type::getHalfTy(Arg->getContext()); in instCombineIntrinsic() local
838 return PoisonValue::get(HalfTy); in instCombineIntrinsic()
840 return UndefValue::get(HalfTy); in instCombineIntrinsic()
847 return ConstantFP::get(HalfTy, Val); in instCombineIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 426 LLT HalfTy = in applyCombineMulCMLT() local
430 Register ZeroVec = B.buildConstant(HalfTy, 0).getReg(0); in applyCombineMulCMLT()
432 B.buildInstr(TargetOpcode::G_BITCAST, {HalfTy}, {SrcReg}).getReg(0); in applyCombineMulCMLT()
434 B.buildICmp(CmpInst::Predicate::ICMP_SLT, HalfTy, CastReg, ZeroVec) in applyCombineMulCMLT()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | AArch64ACLETypes.def | 132 NEON_VECTOR_TYPE(__Float16x4_t, HalfTy, 16, 4, VectorKind::Neon)
145 NEON_VECTOR_TYPE(__Float16x8_t, HalfTy, 16, 8, VectorKind::Neon)
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | LLVMContextImpl.cpp | 35 HalfTy(C, Type::HalfTyID), BFloatTy(C, Type::BFloatTyID), in LLVMContextImpl()
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| H A D | Type.cpp | 283 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
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| H A D | LLVMContextImpl.h | 1759 Type VoidTy, LabelTy, HalfTy, BFloatTy, FloatTy, DoubleTy, MetadataTy,
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| /freebsd/contrib/llvm-project/clang/include/clang/AST/ |
| H A D | BuiltinTypes.def | 201 FLOATING_TYPE(Half, HalfTy)
213 FLOATING_TYPE(Float16, HalfTy)
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5880 const LLT HalfTy, const LLT AmtTy) { in narrowScalarShiftByConstant() argument
5882 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
5883 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
5892 LLT NVT = HalfTy; in narrowScalarShiftByConstant()
5893 unsigned NVTBits = HalfTy.getSizeInBits(); in narrowScalarShiftByConstant()
5992 const LLT HalfTy = LLT::scalar(NewBitSize); in narrowScalarShift() local
5996 return narrowScalarShiftByConstant(MI, VRegAndVal->Value, HalfTy, in narrowScalarShift()
6005 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
6006 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
6020 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift()
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| H A D | CombinerHelper.cpp | 2436 LLT HalfTy = LLT::scalar(HalfSize); in applyCombineShiftToUnmerge() local
2438 auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg); in applyCombineShiftToUnmerge()
2450 Narrowed = Builder.buildLShr(HalfTy, Narrowed, in applyCombineShiftToUnmerge()
2451 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge()
2454 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge()
2463 Narrowed = Builder.buildShl(HalfTy, Narrowed, in applyCombineShiftToUnmerge()
2464 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge()
2467 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge()
2472 HalfTy, Unmerge.getReg(1), in applyCombineShiftToUnmerge()
2473 Builder.buildConstant(HalfTy, HalfSize - 1)); in applyCombineShiftToUnmerge()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.h | 364 LLT HalfTy,
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| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | PrintfFormatString.cpp | 599 return Ctx.HalfTy; in getScalarArgType()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | OpenCLBuiltins.td | 363 def Half : Type<"half", QualType<"Context.HalfTy">>;
372 def "HalfPtr" # AS : PointerType<Type<"__half", QualType<"Context.HalfTy">>, AS>;
373 def "HalfPtrConst" # AS : PointerType<ConstType<Type<"__half", QualType<"Context.HalfTy">>>, AS>;
421 def AtomicHalf : Type<"atomic_half", QualType<"Context.getAtomicType(Context.HalfTy)">>;
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| H A D | SemaARM.cpp | 348 return Context.HalfTy; in getNeonEltType()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/TypeSystem/Clang/ |
| H A D | TypeSystemClang.cpp | 811 if (QualTypeMatchesBitSize(bit_size, ast, ast.HalfTy)) in GetBuiltinTypeForEncodingAndBitSize()
812 return GetType(ast.HalfTy); in GetBuiltinTypeForEncodingAndBitSize()
981 if (QualTypeMatchesBitSize(bit_size, ast, ast.HalfTy)) in GetBuiltinTypeForDWARFEncodingAndBitSize()
982 return GetType(ast.HalfTy); in GetBuiltinTypeForDWARFEncodingAndBitSize()
2065 return ast->HalfTy.getAsOpaquePtr(); in GetOpaqueCompilerType()
4754 else if (bit_size == ast.getTypeSize(ast.HalfTy)) in GetFloatTypeSemantics()
4755 return ast.getFloatTypeSemantics(ast.HalfTy); in GetFloatTypeSemantics()
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