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Searched refs:HalfTy (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCodeGenTypeCache.h39 llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy; member
H A DCGBuiltin.cpp6355 return llvm::FixedVectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad)); in GetNeonType()
6381 return llvm::FixedVectorType::get(CGF->HalfTy, (4 << IsQuad)); in GetFloatNeonType()
7765 Ty = HalfTy; in EmitCommonNeonBuiltinExpr()
8283 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
8290 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
8297 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
8304 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
11682 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::fabs, HalfTy), Ops, "vabs"); in EmitAArch64BuiltinExpr()
11726 llvm::Type *FTy = HalfTy; in EmitAArch64BuiltinExpr()
11751 llvm::Type* FTy = HalfTy; in EmitAArch64BuiltinExpr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h462 MVT HalfTy = typeSplit(Ty).first; in LoHalf() local
464 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in LoHalf()
473 MVT HalfTy = typeSplit(Ty).first; in HiHalf() local
474 SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32); in HiHalf()
475 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in HiHalf()
H A DHexagonISelLoweringHVX.cpp520 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2); in typeSplit() local
521 return { HalfTy, HalfTy }; in typeSplit()
1731 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxConcatVectors()
1732 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors() local
1734 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
2258 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxFpExtend()
2261 getInstr(Hexagon::V6_vconv_sf_qf32, dl, HalfTy, {Pair.first}, DAG); in LowerHvxFpExtend()
2263 getInstr(Hexagon::V6_vconv_sf_qf32, dl, HalfTy, {Pair.second}, DAG); in LowerHvxFpExtend()
2958 MVT HalfTy in SplitVectorOp()
2259 MVT HalfTy = typeSplit(VecTy).first; LowerHvxFpExtend() local
2959 MVT HalfTy = typeSplit(ResTy).first; SplitVectorOp() local
[all...]
H A DHexagonISelDAGToDAGHVX.cpp1192 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), in materialize() local
1196 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1516 MVT HalfTy = getSingleVT(MVT::i8); in packp()
1519 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) }; in packp()
1517 MVT HalfTy = getSingleVT(MVT::i8); packp() local
H A DHexagonISelLowering.cpp2661 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2); in buildVector64() local
2664 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG); in buildVector64()
2667 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG); in buildVector64()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp426 LLT HalfTy = in applyCombineMulCMLT() local
430 Register ZeroVec = B.buildConstant(HalfTy, 0).getReg(0); in applyCombineMulCMLT()
432 B.buildInstr(TargetOpcode::G_BITCAST, {HalfTy}, {SrcReg}).getReg(0); in applyCombineMulCMLT()
434 B.buildICmp(CmpInst::Predicate::ICMP_SLT, HalfTy, CastReg, ZeroVec) in applyCombineMulCMLT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp662 LLT HalfTy, in split64BitValueForMapping() argument
664 assert(HalfTy.getSizeInBits() == 32); in split64BitValueForMapping()
666 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
667 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
2129 LLT HalfTy = LLT::scalar(32); in applyMappingSMULU64() local
2136 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg()); in applyMappingSMULU64()
2138 setRegsToType(MRI, Src0Regs, HalfTy); in applyMappingSMULU64()
2141 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); in applyMappingSMULU64()
2143 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingSMULU64()
2145 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingSMULU64()
[all …]
H A DAMDGPURegisterBankInfo.h128 LLT HalfTy,
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DBuiltinTypes.def201 FLOATING_TYPE(Half, HalfTy)
213 FLOATING_TYPE(Float16, HalfTy)
H A DASTContext.h1142 CanQualType HalfTy; // [OpenCL 6.1.1.1], ARM NEON variable
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DLLVMContextImpl.cpp39 HalfTy(C, Type::HalfTyID), BFloatTy(C, Type::BFloatTyID), in LLVMContextImpl()
H A DType.cpp239 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
H A DLLVMContextImpl.h1583 Type VoidTy, LabelTy, HalfTy, BFloatTy, FloatTy, DoubleTy, MetadataTy,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5191 const LLT HalfTy, const LLT AmtTy) { in narrowScalarShiftByConstant() argument
5193 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
5194 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
5203 LLT NVT = HalfTy; in narrowScalarShiftByConstant()
5204 unsigned NVTBits = HalfTy.getSizeInBits(); in narrowScalarShiftByConstant()
5303 const LLT HalfTy = LLT::scalar(NewBitSize); in narrowScalarShift() local
5307 return narrowScalarShiftByConstant(MI, VRegAndVal->Value, HalfTy, in narrowScalarShift()
5316 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
5317 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
5331 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift()
[all …]
H A DCombinerHelper.cpp2335 LLT HalfTy = LLT::scalar(HalfSize); in applyCombineShiftToUnmerge() local
2337 auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg); in applyCombineShiftToUnmerge()
2349 Narrowed = Builder.buildLShr(HalfTy, Narrowed, in applyCombineShiftToUnmerge()
2350 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge()
2353 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge()
2362 Narrowed = Builder.buildShl(HalfTy, Narrowed, in applyCombineShiftToUnmerge()
2363 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge()
2366 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge()
2371 HalfTy, Unmerge.getReg(1), in applyCombineShiftToUnmerge()
2372 Builder.buildConstant(HalfTy, HalfSize - 1)); in applyCombineShiftToUnmerge()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h337 LLT HalfTy, LLT ShiftAmtTy);
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DPrintfFormatString.cpp599 return Ctx.HalfTy; in getScalarArgType()
H A DASTContext.cpp1444 InitBuiltinType(HalfTy, BuiltinType::Half); in InitBuiltinTypes()
4320 return SVE_ELTTY(HalfTy, 8, 1); in getBuiltinVectorTypeInfo()
4322 return SVE_ELTTY(HalfTy, 8, 2); in getBuiltinVectorTypeInfo()
4324 return SVE_ELTTY(HalfTy, 8, 3); in getBuiltinVectorTypeInfo()
4326 return SVE_ELTTY(HalfTy, 8, 4); in getBuiltinVectorTypeInfo()
11784 Type = Context.HalfTy; in DecodeTypeFromStr()
12600 return HalfTy; in getRealTypeForBitwidth()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DOpenCLBuiltins.td359 def Half : Type<"half", QualType<"Context.HalfTy">>;
368 def "HalfPtr" # AS : PointerType<Type<"__half", QualType<"Context.HalfTy">>, AS>;
369 def "HalfPtrConst" # AS : PointerType<ConstType<Type<"__half", QualType<"Context.HalfTy">>>, AS>;
417 def AtomicHalf : Type<"atomic_half", QualType<"Context.getAtomicType(Context.HalfTy)">>;
H A DSemaARM.cpp381 return Context.HalfTy; in getNeonEltType()
H A DSemaExpr.cpp3824 Ty = Context.HalfTy; in ActOnNumericConstant()
14515 assert((isVector(ResultTy, Context.HalfTy) || in convertHalfVecBinOp()
14518 assert(isVector(LHS.get()->getType(), Context.HalfTy) && in convertHalfVecBinOp()
14519 isVector(RHS.get()->getType(), Context.HalfTy) && in convertHalfVecBinOp()
14581 return VT->getElementType().getCanonicalType() == Ctx.HalfTy; in needsConversionOfHalfVec()
14814 (Opc == BO_Comma || isVector(RHS.get()->getType(), Context.HalfTy) == in CreateBuiltinBinOp()
14815 isVector(LHS.get()->getType(), Context.HalfTy)) && in CreateBuiltinBinOp()
15515 return convertVector(UO, Context.HalfTy, *this); in CreateBuiltinUnaryOp()
H A DSema.cpp439 auto AtomicHalfT = Context.getAtomicType(Context.HalfTy); in Initialize()
/freebsd/contrib/llvm-project/lldb/source/Plugins/TypeSystem/Clang/
H A DTypeSystemClang.cpp791 if (QualTypeMatchesBitSize(bit_size, ast, ast.HalfTy)) in GetBuiltinTypeForEncodingAndBitSize()
792 return GetType(ast.HalfTy); in GetBuiltinTypeForEncodingAndBitSize()
958 if (QualTypeMatchesBitSize(bit_size, ast, ast.HalfTy)) in GetBuiltinTypeForDWARFEncodingAndBitSize()
959 return GetType(ast.HalfTy); in GetBuiltinTypeForDWARFEncodingAndBitSize()
2046 return ast->HalfTy.getAsOpaquePtr(); in GetOpaqueCompilerType()
4723 else if (bit_size == ast.getTypeSize(ast.HalfTy)) in GetFloatTypeSemantics()
4724 return ast.getFloatTypeSemantics(ast.HalfTy); in GetFloatTypeSemantics()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp15886 auto *HalfTy = HalfV->getType(); in areExtractShuffleVectors() local
15888 2 * HalfTy->getPrimitiveSizeInBits().getFixedValue(); in areExtractShuffleVectors()
28527 auto *HalfTy = VectorType::getHalfElementsVectorType(Ty); in createComplexDeinterleavingIR() local
28528 auto *LowerSplitA = B.CreateExtractVector(HalfTy, InputA, B.getInt64(0)); in createComplexDeinterleavingIR()
28529 auto *LowerSplitB = B.CreateExtractVector(HalfTy, InputB, B.getInt64(0)); in createComplexDeinterleavingIR()
28531 B.CreateExtractVector(HalfTy, InputA, B.getInt64(Stride)); in createComplexDeinterleavingIR()
28533 B.CreateExtractVector(HalfTy, InputB, B.getInt64(Stride)); in createComplexDeinterleavingIR()
28537 LowerSplitAcc = B.CreateExtractVector(HalfTy, Accumulator, B.getInt64(0)); in createComplexDeinterleavingIR()
28539 B.CreateExtractVector(HalfTy, Accumulator, B.getInt64(Stride)); in createComplexDeinterleavingIR()

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