| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/ |
| H A D | XtensaMCTargetDesc.cpp | 78 bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits, in checkRegister() argument
82 return FeatureBits[Xtensa::FeatureBoolean]; in checkRegister()
85 if (FeatureBits[Xtensa::FeatureTimers1]) in checkRegister()
89 if (FeatureBits[Xtensa::FeatureTimers2]) in checkRegister()
93 if (FeatureBits[Xtensa::FeatureTimers3]) in checkRegister()
101 return FeatureBits[Xtensa::FeatureCoprocessor]; in checkRegister()
103 return RAType == Xtensa::REGISTER_READ && FeatureBits[Xtensa::FeatureDebug]; in checkRegister()
109 return FeatureBits[Xtensa::FeatureException]; in checkRegister()
114 if (FeatureBits[Xtensa::FeatureHighPriInterrupts]) in checkRegister()
120 if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel3]) in checkRegister()
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| H A D | XtensaMCTargetDesc.h | 65 bool checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 232 FeatureBits = in InitMCProcessorInfo()
244 FeatureBits = in setDefaultFeatures()
263 FeatureBits.flip(FB); in ToggleFeature()
264 return FeatureBits; in ToggleFeature()
268 FeatureBits ^= FB; in ToggleFeature()
269 return FeatureBits; in ToggleFeature()
274 SetImpliedBits(FeatureBits, FB, ProcFeatures); in SetFeatureBitsTransitively()
275 return FeatureBits; in SetFeatureBitsTransitively()
282 FeatureBits.reset(I); in ClearFeatureBitsTransitively()
283 ClearImpliedBits(FeatureBits, I, ProcFeatures); in ClearFeatureBitsTransitively()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.cpp | 65 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, in computeTargetABI() argument
69 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE]; in computeTargetABI()
99 FeatureBits[RISCV::FeatureStdExtD]) in computeTargetABI()
106 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
138 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument
139 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate()
141 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) in validate()
143 if (FeatureBits[RISCV::Feature32Bit] && in validate()
144 FeatureBits[RISCV::Feature64Bit]) in validate()
149 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
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| H A D | RISCVBaseInfo.h | 210 getTailExpandUseRegNo(const FeatureBitset &FeatureBits) { in getTailExpandUseRegNo() argument
213 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6; in getTailExpandUseRegNo()
570 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
587 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
590 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchBaseInfo.cpp | 75 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, in computeTargetABI() argument
88 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
90 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
94 return Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
96 return Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
164 if (FeatureBits[LoongArch::FeatureBasicD]) in computeTargetABI()
166 if (FeatureBits[LoongArch::FeatureBasicF]) in computeTargetABI()
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| H A D | LoongArchBaseInfo.h | 129 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 94 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
115 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()
117 FeatureBits = FeatureBits_; in setFeatureBits()
123 return FeatureBits[Feature]; in hasFeature()
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | AArch64TargetParser.cpp | 60 ExtensionSet FeatureBits; in getFMVPriority() local
68 FeatureBits.enable(*FMV->ID); in getFMVPriority()
74 if (Info.ID && FeatureBits.Enabled.test(*Info.ID)) in getFMVPriority()
82 ExtensionSet FeatureBits; in getCpuSupportsMask() local
86 FeatureBits.enable(*Info->ID); in getCpuSupportsMask()
91 if (Info.ID && FeatureBits.Enabled.test(*Info.ID)) in getCpuSupportsMask()
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| /freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | AArch64.cpp | 1253 llvm::AArch64::ExtensionSet &FeatureBits) { in parseTargetAttr() argument
1257 if (FeatureBits.parseModifier(Feature)) in parseTargetAttr()
1272 llvm::AArch64::ExtensionSet FeatureBits; in parseTargetAttr() local
1274 FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten, in parseTargetAttr()
1299 FeatureBits.addArchDefaults(*AI); in parseTargetAttr()
1301 SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits); in parseTargetAttr()
1312 FeatureBits.addCPUDefaults(*CpuInfo); in parseTargetAttr()
1313 SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits); in parseTargetAttr()
1322 SplitAndAddFeatures(Feature, Ret.Features, FeatureBits); in parseTargetAttr()
1324 if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true)) in parseTargetAttr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 163 FeatureBitset FeatureBits = getFeatureBits(); in initializeSubtargetDependencies() local
165 setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex)); in initializeSubtargetDependencies()
166 setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits)); in initializeSubtargetDependencies()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 215 const FeatureBitset &FeatureBits = in DecodeGPRPairRegisterClass() local
217 bool hasHighReg = FeatureBits[CSKY::FeatureHighreg]; in DecodeGPRPairRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 922 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local
949 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
2555 const FeatureBitset &FeatureBits = in DecodeHINTInstruction() local
2567 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2800 const FeatureBitset &FeatureBits = in DecodeSETPANInstruction() local
2803 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2804 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4840 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local
4847 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4985 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 910 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
911 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
917 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
927 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 276 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
277 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
278 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
1966 const auto &FeatureBits = getSTI().getFeatureBits(); in parseCSRSystemRegister() local
1967 if (!SysReg->haveRequiredFeatures(FeatureBits)) { in parseCSRSystemRegister()
1972 if (SysReg->IsRV32Only && FeatureBits[RISCV::Feature64Bit]) { in parseCSRSystemRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 122 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
123 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
124 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
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| /freebsd/sys/dev/aac/ |
| H A D | aacreg.h | 639 u_int32_t FeatureBits; member
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| /freebsd/sys/dev/aacraid/ |
| H A D | aacraid_reg.h | 615 u_int32_t FeatureBits; member
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| H A D | aacraid.c | 2509 sc->aac_feature_bits = le32toh(supp_info->FeatureBits); in aac_describe_controller()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 471 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch() local
472 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch()
473 STI.setFeatureBits(FeatureBits); in selectArch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5407 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); in getMClassRegisterMask() local
5408 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits)) in getMClassRegisterMask()
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| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | ASTContext.cpp | 14881 llvm::AArch64::ExtensionSet FeatureBits; in getFMVBackendFeaturesFor() local
14885 FeatureBits.enable(*FMVExt->ID); in getFMVBackendFeaturesFor()
14886 FeatureBits.toLLVMFeatureList(BackendFeats); in getFMVBackendFeaturesFor()
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