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Searched refs:FeatureBits (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSubtargetInfo.cpp211 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
222 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures()
242 FeatureBits.flip(FB); in ToggleFeature()
243 return FeatureBits; in ToggleFeature()
247 FeatureBits ^= FB; in ToggleFeature()
248 return FeatureBits; in ToggleFeature()
253 SetImpliedBits(FeatureBits, FB, ProcFeatures); in SetFeatureBitsTransitively()
254 return FeatureBits; in SetFeatureBitsTransitively()
261 FeatureBits.reset(I); in ClearFeatureBitsTransitively()
262 ClearImpliedBits(FeatureBits, I, ProcFeatures); in ClearFeatureBitsTransitively()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp38 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, in computeTargetABI() argument
42 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE]; in computeTargetABI()
72 FeatureBits[RISCV::FeatureStdExtD]) in computeTargetABI()
79 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
111 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument
112 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate()
114 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) in validate()
116 if (FeatureBits[RISCV::Feature32Bit] && in validate()
117 FeatureBits[RISCV::Feature64Bit]) in validate()
122 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
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H A DRISCVBaseInfo.h461 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
478 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
481 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchBaseInfo.cpp72 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, in computeTargetABI() argument
85 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
87 return !Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
91 return Is64Bit && FeatureBits[LoongArch::FeatureBasicF]; in computeTargetABI()
93 return Is64Bit && FeatureBits[LoongArch::FeatureBasicD]; in computeTargetABI()
161 if (FeatureBits[LoongArch::FeatureBasicD]) in computeTargetABI()
163 if (FeatureBits[LoongArch::FeatureBasicF]) in computeTargetABI()
H A DLoongArchBaseInfo.h72 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h92 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
112 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()
114 FeatureBits = FeatureBits_; in setFeatureBits()
120 return FeatureBits[Feature]; in hasFeature()
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DAArch64.cpp1139 llvm::AArch64::ExtensionSet &FeatureBits) { in parseTargetAttr() argument
1143 if (FeatureBits.parseModifier(Feature)) in parseTargetAttr()
1158 llvm::AArch64::ExtensionSet FeatureBits; in parseTargetAttr() local
1160 FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten, in parseTargetAttr()
1185 FeatureBits.addArchDefaults(*AI); in parseTargetAttr()
1187 SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits); in parseTargetAttr()
1198 FeatureBits.addCPUDefaults(*CpuInfo); in parseTargetAttr()
1199 SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits); in parseTargetAttr()
1208 SplitAndAddFeatures(Feature, Ret.Features, FeatureBits); in parseTargetAttr()
1210 if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true)) in parseTargetAttr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp164 FeatureBitset FeatureBits = getFeatureBits(); in initializeSubtargetDependencies() local
166 setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex)); in initializeSubtargetDependencies()
167 setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits)); in initializeSubtargetDependencies()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp215 const FeatureBitset &FeatureBits = in DecodeGPRPairRegisterClass() local
217 bool hasHighReg = FeatureBits[CSKY::FeatureHighreg]; in DecodeGPRPairRegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp922 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local
949 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
2550 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeHINTInstruction() local
2561 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2795 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local
2797 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2798 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4834 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local
4841 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4979 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp912 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
913 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
919 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
929 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
/freebsd/sys/dev/aac/
H A Daacreg.h639 u_int32_t FeatureBits; member
/freebsd/sys/dev/aacraid/
H A Daacraid_reg.h615 u_int32_t FeatureBits; member
H A Daacraid.c2509 sc->aac_feature_bits = le32toh(supp_info->FeatureBits); in aac_describe_controller()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp267 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
268 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
269 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp473 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch() local
474 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch()
475 STI.setFeatureBits(FeatureBits); in selectArch()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp5423 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); in getMClassRegisterMask() local
5424 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits)) in getMClassRegisterMask()