1bdd1243dSDimitry Andric //===-- XtensaMCTargetDesc.cpp - Xtensa target descriptions ---------------===//
2bdd1243dSDimitry Andric //
3bdd1243dSDimitry Andric // The LLVM Compiler Infrastructure
4bdd1243dSDimitry Andric //
5bdd1243dSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6bdd1243dSDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
7bdd1243dSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8bdd1243dSDimitry Andric //
9bdd1243dSDimitry Andric //===----------------------------------------------------------------------===//
10bdd1243dSDimitry Andric #include "XtensaMCTargetDesc.h"
11*0fca6ea1SDimitry Andric #include "TargetInfo/XtensaTargetInfo.h"
12bdd1243dSDimitry Andric #include "XtensaInstPrinter.h"
13bdd1243dSDimitry Andric #include "XtensaMCAsmInfo.h"
14*0fca6ea1SDimitry Andric #include "XtensaTargetStreamer.h"
15bdd1243dSDimitry Andric #include "llvm/ADT/STLExtras.h"
16bdd1243dSDimitry Andric #include "llvm/MC/MCAsmInfo.h"
17bdd1243dSDimitry Andric #include "llvm/MC/MCInstrInfo.h"
18bdd1243dSDimitry Andric #include "llvm/MC/MCRegisterInfo.h"
19bdd1243dSDimitry Andric #include "llvm/MC/MCStreamer.h"
20bdd1243dSDimitry Andric #include "llvm/MC/MCSubtargetInfo.h"
21bdd1243dSDimitry Andric #include "llvm/MC/TargetRegistry.h"
22bdd1243dSDimitry Andric #include "llvm/Support/ErrorHandling.h"
23bdd1243dSDimitry Andric
24bdd1243dSDimitry Andric #define GET_INSTRINFO_MC_DESC
25bdd1243dSDimitry Andric #include "XtensaGenInstrInfo.inc"
26bdd1243dSDimitry Andric
27bdd1243dSDimitry Andric #define GET_REGINFO_MC_DESC
28bdd1243dSDimitry Andric #include "XtensaGenRegisterInfo.inc"
29bdd1243dSDimitry Andric
30bdd1243dSDimitry Andric #define GET_SUBTARGETINFO_MC_DESC
31bdd1243dSDimitry Andric #include "XtensaGenSubtargetInfo.inc"
32bdd1243dSDimitry Andric
33bdd1243dSDimitry Andric using namespace llvm;
34bdd1243dSDimitry Andric
createXtensaMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT,const MCTargetOptions & Options)35bdd1243dSDimitry Andric static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI,
36bdd1243dSDimitry Andric const Triple &TT,
37bdd1243dSDimitry Andric const MCTargetOptions &Options) {
38bdd1243dSDimitry Andric MCAsmInfo *MAI = new XtensaMCAsmInfo(TT);
39bdd1243dSDimitry Andric return MAI;
40bdd1243dSDimitry Andric }
41bdd1243dSDimitry Andric
createXtensaMCInstrInfo()42bdd1243dSDimitry Andric static MCInstrInfo *createXtensaMCInstrInfo() {
43bdd1243dSDimitry Andric MCInstrInfo *X = new MCInstrInfo();
44bdd1243dSDimitry Andric InitXtensaMCInstrInfo(X);
45bdd1243dSDimitry Andric return X;
46bdd1243dSDimitry Andric }
47bdd1243dSDimitry Andric
createXtensaMCInstPrinter(const Triple & TT,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)48bdd1243dSDimitry Andric static MCInstPrinter *createXtensaMCInstPrinter(const Triple &TT,
49bdd1243dSDimitry Andric unsigned SyntaxVariant,
50bdd1243dSDimitry Andric const MCAsmInfo &MAI,
51bdd1243dSDimitry Andric const MCInstrInfo &MII,
52bdd1243dSDimitry Andric const MCRegisterInfo &MRI) {
53bdd1243dSDimitry Andric return new XtensaInstPrinter(MAI, MII, MRI);
54bdd1243dSDimitry Andric }
55bdd1243dSDimitry Andric
createXtensaMCRegisterInfo(const Triple & TT)56bdd1243dSDimitry Andric static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) {
57bdd1243dSDimitry Andric MCRegisterInfo *X = new MCRegisterInfo();
58bdd1243dSDimitry Andric InitXtensaMCRegisterInfo(X, Xtensa::SP);
59bdd1243dSDimitry Andric return X;
60bdd1243dSDimitry Andric }
61bdd1243dSDimitry Andric
62bdd1243dSDimitry Andric static MCSubtargetInfo *
createXtensaMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)63bdd1243dSDimitry Andric createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
64bdd1243dSDimitry Andric return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS);
65bdd1243dSDimitry Andric }
66bdd1243dSDimitry Andric
67*0fca6ea1SDimitry Andric static MCTargetStreamer *
createXtensaAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint)68*0fca6ea1SDimitry Andric createXtensaAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
69*0fca6ea1SDimitry Andric MCInstPrinter *InstPrint) {
70*0fca6ea1SDimitry Andric return new XtensaTargetAsmStreamer(S, OS);
71*0fca6ea1SDimitry Andric }
72*0fca6ea1SDimitry Andric
73*0fca6ea1SDimitry Andric static MCTargetStreamer *
createXtensaObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)74*0fca6ea1SDimitry Andric createXtensaObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
75*0fca6ea1SDimitry Andric return new XtensaTargetELFStreamer(S);
76*0fca6ea1SDimitry Andric }
77*0fca6ea1SDimitry Andric
LLVMInitializeXtensaTargetMC()78bdd1243dSDimitry Andric extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() {
79bdd1243dSDimitry Andric // Register the MCAsmInfo.
80*0fca6ea1SDimitry Andric TargetRegistry::RegisterMCAsmInfo(getTheXtensaTarget(),
81*0fca6ea1SDimitry Andric createXtensaMCAsmInfo);
82bdd1243dSDimitry Andric
83bdd1243dSDimitry Andric // Register the MCCodeEmitter.
84bdd1243dSDimitry Andric TargetRegistry::RegisterMCCodeEmitter(getTheXtensaTarget(),
85bdd1243dSDimitry Andric createXtensaMCCodeEmitter);
86bdd1243dSDimitry Andric
87bdd1243dSDimitry Andric // Register the MCInstrInfo.
88*0fca6ea1SDimitry Andric TargetRegistry::RegisterMCInstrInfo(getTheXtensaTarget(),
89*0fca6ea1SDimitry Andric createXtensaMCInstrInfo);
90bdd1243dSDimitry Andric
91bdd1243dSDimitry Andric // Register the MCInstPrinter.
92bdd1243dSDimitry Andric TargetRegistry::RegisterMCInstPrinter(getTheXtensaTarget(),
93bdd1243dSDimitry Andric createXtensaMCInstPrinter);
94bdd1243dSDimitry Andric
95bdd1243dSDimitry Andric // Register the MCRegisterInfo.
96bdd1243dSDimitry Andric TargetRegistry::RegisterMCRegInfo(getTheXtensaTarget(),
97bdd1243dSDimitry Andric createXtensaMCRegisterInfo);
98bdd1243dSDimitry Andric
99bdd1243dSDimitry Andric // Register the MCSubtargetInfo.
100bdd1243dSDimitry Andric TargetRegistry::RegisterMCSubtargetInfo(getTheXtensaTarget(),
101bdd1243dSDimitry Andric createXtensaMCSubtargetInfo);
102bdd1243dSDimitry Andric
103bdd1243dSDimitry Andric // Register the MCAsmBackend.
104bdd1243dSDimitry Andric TargetRegistry::RegisterMCAsmBackend(getTheXtensaTarget(),
105bdd1243dSDimitry Andric createXtensaMCAsmBackend);
106*0fca6ea1SDimitry Andric
107*0fca6ea1SDimitry Andric // Register the asm target streamer.
108*0fca6ea1SDimitry Andric TargetRegistry::RegisterAsmTargetStreamer(getTheXtensaTarget(),
109*0fca6ea1SDimitry Andric createXtensaAsmTargetStreamer);
110*0fca6ea1SDimitry Andric
111*0fca6ea1SDimitry Andric // Register the ELF target streamer.
112*0fca6ea1SDimitry Andric TargetRegistry::RegisterObjectTargetStreamer(
113*0fca6ea1SDimitry Andric getTheXtensaTarget(), createXtensaObjectTargetStreamer);
114bdd1243dSDimitry Andric }
115