1*bdd1243dSDimitry Andric //===-- XtensaMCTargetDesc.h - Xtensa Target Descriptions -------*- C++ -*-===// 2*bdd1243dSDimitry Andric // 3*bdd1243dSDimitry Andric // The LLVM Compiler Infrastructure 4*bdd1243dSDimitry Andric // 5*bdd1243dSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6*bdd1243dSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 7*bdd1243dSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8*bdd1243dSDimitry Andric // 9*bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 10*bdd1243dSDimitry Andric // 11*bdd1243dSDimitry Andric // This file provides Xtensa specific target descriptions. 12*bdd1243dSDimitry Andric // 13*bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 14*bdd1243dSDimitry Andric 15*bdd1243dSDimitry Andric #ifndef LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H 16*bdd1243dSDimitry Andric #define LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H 17*bdd1243dSDimitry Andric #include "llvm/Support/DataTypes.h" 18*bdd1243dSDimitry Andric #include <memory> 19*bdd1243dSDimitry Andric 20*bdd1243dSDimitry Andric namespace llvm { 21*bdd1243dSDimitry Andric 22*bdd1243dSDimitry Andric class MCAsmBackend; 23*bdd1243dSDimitry Andric class MCCodeEmitter; 24*bdd1243dSDimitry Andric class MCContext; 25*bdd1243dSDimitry Andric class MCInstrInfo; 26*bdd1243dSDimitry Andric class MCObjectTargetWriter; 27*bdd1243dSDimitry Andric class MCObjectWriter; 28*bdd1243dSDimitry Andric class MCRegisterInfo; 29*bdd1243dSDimitry Andric class MCSubtargetInfo; 30*bdd1243dSDimitry Andric class MCTargetOptions; 31*bdd1243dSDimitry Andric class StringRef; 32*bdd1243dSDimitry Andric class Target; 33*bdd1243dSDimitry Andric class raw_ostream; 34*bdd1243dSDimitry Andric 35*bdd1243dSDimitry Andric extern Target TheXtensaTarget; 36*bdd1243dSDimitry Andric 37*bdd1243dSDimitry Andric MCCodeEmitter *createXtensaMCCodeEmitter(const MCInstrInfo &MCII, 38*bdd1243dSDimitry Andric MCContext &Ctx); 39*bdd1243dSDimitry Andric 40*bdd1243dSDimitry Andric MCAsmBackend *createXtensaMCAsmBackend(const Target &T, 41*bdd1243dSDimitry Andric const MCSubtargetInfo &STI, 42*bdd1243dSDimitry Andric const MCRegisterInfo &MRI, 43*bdd1243dSDimitry Andric const MCTargetOptions &Options); 44*bdd1243dSDimitry Andric std::unique_ptr<MCObjectTargetWriter> 45*bdd1243dSDimitry Andric createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian); 46*bdd1243dSDimitry Andric } // end namespace llvm 47*bdd1243dSDimitry Andric 48*bdd1243dSDimitry Andric // Defines symbolic names for Xtensa registers. 49*bdd1243dSDimitry Andric // This defines a mapping from register name to register number. 50*bdd1243dSDimitry Andric #define GET_REGINFO_ENUM 51*bdd1243dSDimitry Andric #include "XtensaGenRegisterInfo.inc" 52*bdd1243dSDimitry Andric 53*bdd1243dSDimitry Andric // Defines symbolic names for the Xtensa instructions. 54*bdd1243dSDimitry Andric #define GET_INSTRINFO_ENUM 55*bdd1243dSDimitry Andric #include "XtensaGenInstrInfo.inc" 56*bdd1243dSDimitry Andric 57*bdd1243dSDimitry Andric #define GET_SUBTARGETINFO_ENUM 58*bdd1243dSDimitry Andric #include "XtensaGenSubtargetInfo.inc" 59*bdd1243dSDimitry Andric 60*bdd1243dSDimitry Andric #endif // LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAMCTARGETDESC_H 61