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Searched refs:FPR16 (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfh.td42 f16, FPR16, FPR32, ?, FPR16>;
44 f16, FPR16, FPR32, ?, FPR16>;
46 ?, ?, FPR32, FPR64, FPR16>;
48 ?, ?, FPR32, FPR64, FPR16>;
79 def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>;
84 def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>;
152 def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">,
156 def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,
204 def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;
205 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
[all …]
H A DRISCVInstrInfoZfa.td142 def FLI_H : FPFLI_r<0b1111010, 0b00001, 0b000, FPR16, "fli.h">,
147 def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, Commutable=1>;
148 def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, Commutable=1>;
151 def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">,
153 def FROUNDNX_H : FPUnaryOp_r_frm<0b0100010, 0b00101, FPR16, FPR16, "froundnx.h">,
157 def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16>;
158 def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
182 (FLTQ_H GPR:$rd, FPR16
[all...]
H A DRISCVInstrInfoZfbfmin.td35 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
37 def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
50 def : StPat<store, FSH, FPR16, bf16>;
56 def : Pat<(riscv_fpextend_bf16 (bf16 FPR16:$rs1)),
57 (FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;
61 def : Pat<(riscv_fmv_x_anyexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
62 def : Pat<(riscv_fmv_x_signexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
68 def : Pat<(i32 (any_fp_to_sint (bf16 FPR16
[all...]
H A DRISCVScheduleXSf.td29 foreach f = ["FPR16", "FPR32", "FPR64"] in {
53 foreach f = ["FPR16", "FPR32", "FPR64"] in {
H A DRISCVInstrInfoVPseudos.td115 ["FPR16", "F"],
270 !eq(Scal, f16) : "FPR16",
271 !eq(Scal, bf16) : "FPR16",
321 def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, V_MF4, f16, FPR16>;
322 def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, V_MF2, f16, FPR16>;
325 def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, V_M1, f16, FPR16>;
332 V_M2, f16, FPR16>;
334 V_M4, f16, FPR16>;
336 V_M8, f16, FPR16>;
357 def VBF16MF4: VTypeInfo<vbfloat16mf4_t, vbool64_t, 16, V_MF4, bf16, FPR16>;
[all …]
H A DRISCVInstrInfoXSf.td711 RegisterClass ScalarRegClass = !cond(!eq(Sew, 16) : FPR16,
715 string ScalarSuffix = !cond(!eq(Scalar, f16) : "FPR16",
H A DRISCVRegisterInfo.td250 def FPR16 : RISCVRegisterClass<[f16, bf16], 16, (add
H A DRISCVSchedSiFive7.td990 foreach f = ["FPR16", "FPR32", "FPR64"] in {
1006 foreach f = ["FPR16", "FPR32", "FPR64"] in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4958 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
4959 [(set GPR32:$Rd, (OpN (f16 FPR16:$Rn)))]> {
4965 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
4966 [(set GPR64:$Rd, (OpN (f16 FPR16:$Rn)))]> {
4999 def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32,
5001 [(set GPR32:$Rd, (OpN (fmul (f16 FPR16:$Rn),
5009 def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64,
5011 [(set GPR64:$Rd, (OpN (fmul (f16 FPR16:$Rn),
5094 def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
5110 def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
[all …]
H A DAArch64InstrInfo.td4213 (STRHui FPR16:$Rt, GPR64sp:$Rn, uimm12s2:$offset)>;
4348 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9:$offset)>;
4574 def : Pat<(post_store (bf16 FPR16:$Rt), GPR64sp:$addr, simm9:$off),
4575 (STRHpost FPR16:$Rt, GPR64sp:$addr, simm9:$off)>;
4877 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
4886 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
4921 def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))),
4922 (cvt_bf16_to_fp32 FPR16:$Rn)>;
4924 def : Pat<(f64 (any_fpextend (bf16 FPR16:$Rn))),
4925 (FCVTDSr (f32 (cvt_bf16_to_fp32 FPR16:$Rn)))>;
[all …]
H A DAArch64SVEInstrInfo.td820 def : Pat<(nxv8f16 (splat_vector (f16 FPR16:$src))),
821 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
822 def : Pat<(nxv4f16 (splat_vector (f16 FPR16:$src))),
823 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
824 def : Pat<(nxv2f16 (splat_vector (f16 FPR16:$src))),
825 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
832 def : Pat<(nxv8bf16 (splat_vector (bf16 FPR16:$src))),
833 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
834 def : Pat<(nxv4bf16 (splat_vector (bf16 FPR16:$src))),
835 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
[all …]
H A DAArch64RegisterInfo.td456 def FPR16 : RegisterClass<"AArch64", [f16, bf16, i16], 16, (sequence "H%u", 0, 31)> {
461 def FPR16_lo : RegisterClass<"AArch64", [f16], 16, (trunc FPR16, 16)> {
717 def FPR16Op : RegisterOperand<FPR16, "printOperand"> {
718 let ParserMatchClass = FPRAsmOperand<"FPR16">;
H A DAArch64SMEInstrInfo.td205 defm _FPR16 : CoalescerBarrierPseudo<FPR16, [bf16, f16]>;
H A DSVEInstrFormats.td6915 def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>;
7024 def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>;
7233 def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
7240 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp307 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; in isHForm() local
309 return Op.isReg() && FPR16.contains(Op.getReg()); in isHForm()
324 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; in isFpOrNEON() local
332 FPR16.contains(Reg) || FPR8.contains(Reg); in isFpOrNEON()