Lines Matching refs:FPR16
4958 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
4959 [(set GPR32:$Rd, (OpN (f16 FPR16:$Rn)))]> {
4965 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
4966 [(set GPR64:$Rd, (OpN (f16 FPR16:$Rn)))]> {
4999 def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32,
5001 [(set GPR32:$Rd, (OpN (fmul (f16 FPR16:$Rn),
5009 def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64,
5011 [(set GPR64:$Rd, (OpN (fmul (f16 FPR16:$Rn),
5094 def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
5110 def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
5127 def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_recip_f16_i32, asm,
5128 [(set (f16 FPR16:$Rd),
5155 def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_recip_f16_i64, asm,
5156 [(set (f16 FPR16:$Rd),
5250 def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> {
5256 def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> {
5272 def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> {
5278 def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> {
5329 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
5330 [(set (f16 FPR16:$Rd), (any_fpround FPR64:$Rn))]>;
5337 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
5338 [(set FPR64:$Rd, (any_fpextend (f16 FPR16:$Rn)))]>;
5341 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
5342 [(set FPR32:$Rd, (any_fpextend (f16 FPR16:$Rn)))]>;
5349 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
5350 [(set (f16 FPR16:$Rd), (any_fpround FPR32:$Rn))]>;
5377 def Hr : BaseSingleOperandFPData<{0b00,opcode}, FPR16, f16, asm, node> {
5437 def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
5438 [(set (f16 FPR16:$Rd),
5439 (node (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]> {
5459 def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
5460 [(set (f16 FPR16:$Rd), (fneg (node (f16 FPR16:$Rn), (f16 FPR16:$Rm))))]> {
5502 def Hrrr : BaseThreeOperandFPData<isNegated, isSub, FPR16, asm,
5503 [(set (f16 FPR16:$Rd),
5504 (node (f16 FPR16:$Rn), (f16 FPR16:$Rm), (f16 FPR16:$Ra)))]> {
5522 def : Pat<(f16 (node (f16 FPR16:$Rn),
5524 (f16 FPR16:$Ra))),
5526 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
5529 (f16 FPR16:$Rm),
5530 (f16 FPR16:$Ra))),
5532 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>;
5602 def Hrr : BaseTwoOperandFPComparison<signalAllNans, FPR16, asm,
5603 [(OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)), (implicit NZCV)]> {
5608 def Hri : BaseOneOperandFPComparison<signalAllNans, FPR16, asm,
5609 [(OpNode (f16 FPR16:$Rn), fpimm0), (implicit NZCV)]> {
5666 def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic,
5667 [(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm), (i32 imm:$nzcv),
5713 def Hrrr : BaseFPCondSelect<FPR16, f16, asm> {
5746 def Hi : BaseFPMoveImmediate<FPR16, fpimm16, asm> {
7370 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
7383 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
7390 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
7391 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
7406 def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
7407 [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]>;
7423 def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
7457 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
7469 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
7575 def v1i16rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
7585 (!cast<Instruction>(NAME # v1i16rz) FPR16:$Rd, FPR16:$Rn), 0>;
7611 def v1f16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
7625 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
7626 [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn)))]>;
7637 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
7652 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
7667 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
7668 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
7743 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
7745 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
7752 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
7754 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
7768 def v4i16v : BaseSIMDAcrossLanes<0, 0, {sz1, 0}, opcode, FPR16, V64,
7770 [(set (f16 FPR16:$Rd), (intOp (v4f16 V64:$Rn)))]>;
7771 def v8i16v : BaseSIMDAcrossLanes<1, 0, {sz1, 0}, opcode, FPR16, V128,
7773 [(set (f16 FPR16:$Rd), (intOp (v8f16 V128:$Rn)))]>;
8311 def i16 : BaseSIMDScalarDUP<FPR16, V128, asm, ".h", VectorIndexH> {
8337 FPR16, V128, VectorIndexH>;
8694 : I<(outs FPR16:$Rd), (ins FPR32:$Rn), asm, "\t$Rd, $Rn", "",
8695 [(set (bf16 FPR16:$Rd), (int_aarch64_neon_bfcvt (f32 FPR32:$Rn)))]>,
8970 def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
8972 (!cast<Instruction>(INST # "v1i16_indexed") FPR16:$Rd, FPR16:$Rn,
9679 FPR16, FPR16, vecshiftR16, asm, []> {
9746 FPR8, FPR16, vecshiftR8, asm, []> {
9751 FPR16, FPR32, vecshiftR16, asm, []> {
9770 FPR16, FPR16, vecshiftL16, asm, []> {
9797 FPR16, FPR16, vecshiftR16, asm, []> {