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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp129 : FP(P), TRI(T) {} in PrintFP()
131 const FlowPattern &FP; member
138 OS << "{ SplitB:" << PrintMB(P.FP.SplitB) in operator <<()
139 << ", PredR:" << printReg(P.FP.PredR, &P.TRI) in operator <<()
140 << ", TrueB:" << PrintMB(P.FP.TrueB) in operator <<()
141 << ", FalseB:" << PrintMB(P.FP.FalseB) in operator <<()
142 << ", JoinB:" << PrintMB(P.FP.JoinB) << " }"; in operator <<()
171 FlowPattern &FP);
179 bool isValid(const FlowPattern &FP) const;
182 const FlowPattern &FP) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleV6.td194 // FP Special Register to Integer Register File Move
197 // Single-precision FP Unary
200 // Double-precision FP Unary
203 // Single-precision FP Compare
206 // Double-precision FP Compare
209 // Single to Double FP Convert
212 // Double to Single FP Convert
215 // Single-Precision FP to Integer Convert
218 // Double-Precision FP to Integer Convert
221 // Integer to Single-Precision FP Convert
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H A DARMScheduleA8.td252 // FP Special Register to Integer Register File Move
256 // Single-precision FP Unary
260 // Double-precision FP Unary
265 // Single-precision FP Compare
269 // Double-precision FP Compare
274 // Single to Double FP Convert
279 // Double to Single FP Convert
284 // Single-Precision FP to Integer Convert
288 // Double-Precision FP to Integer Convert
293 // Integer to Single-Precision FP Convert
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/freebsd/crypto/krb5/src/lib/crypto/builtin/des/
H A Df_tables.h51 #define FP des_FP_table macro
200 (left) = (FP[((right) >> 24) & 0xff] << 6) \
201 | (FP[((right) >> 16) & 0xff] << 4) \
202 | (FP[((right) >> 8) & 0xff] << 2) \
203 | FP[(right) & 0xff]; \
204 (right) = (FP[((temp) >> 24) & 0xff] << 6) \
205 | (FP[((temp) >> 16) & 0xff] << 4) \
206 | (FP[((temp) >> 8) & 0xff] << 2) \
207 | FP[temp & 0xff]; \
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetOptionsImpl.cpp30 StringRef FP = FPAttr.getValueAsString(); in DisableFramePointerElim() local
31 if (FP == "all") in DisableFramePointerElim()
33 if (FP == "non-leaf") in DisableFramePointerElim()
35 if (FP == "none" || FP == "reserved") in DisableFramePointerElim()
H A DRegisterUsageInfo.cpp60 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
61 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
65 PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) { in getRegUsageInfo() argument
66 auto It = RegMasks.find(&FP); in getRegUsageInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN1.td48 def N1UnitV0 : ProcResource<1>; // FP/ASIMD 0
49 def N1UnitV1 : ProcResource<1>; // FP/ASIMD 1
52 def N1UnitV : ProcResGroup<[N1UnitV0, N1UnitV1]>; // FP/ASIMD units
400 // FP data processing instructions
403 // FP absolute value
404 // FP arithmetic
405 // FP min/max
406 // FP negate
407 // FP select
410 // FP compar
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H A DAArch64SchedThunderX3T110.td57 // Port 6: FP/Neon/SIMD/Crypto.
60 // Port 7: FP/Neon/SIMD/Crypto.
63 // Port 8: FP/Neon/SIMD/Crypto.
66 // Port 9: FP/Neon/SIMD/Crypto.
91 // FP micro-ops on ports FP0/FP1/FP2/FP3.
95 // FP micro-ops on ports FP2/FP3.
849 // 3.10 FP Load Instructions
1028 // 3.11 FP Store Instructions
1198 // 3.8 FP Data Processing Instructions
1201 // FP absolut
[all...]
H A DAArch64SchedNeoverseV1.td54 def V1UnitV0 : ProcResource<1>; // FP/ASIMD 0
55 def V1UnitV1 : ProcResource<1>; // FP/ASIMD 1
56 def V1UnitV2 : ProcResource<1>; // FP/ASIMD 2
57 def V1UnitV3 : ProcResource<1>; // FP/ASIMD 3
65 V1UnitV2, V1UnitV3]>; // FP/ASIMD units
66 def V1UnitV01 : ProcResGroup<[V1UnitV0, V1UnitV1]>; // FP/ASIMD 0/1 units
67 def V1UnitV02 : ProcResGroup<[V1UnitV0, V1UnitV2]>; // FP/ASIMD 0/2 units
68 def V1UnitV13 : ProcResGroup<[V1UnitV1, V1UnitV3]>; // FP/ASIMD 1/3 units
739 // FP data processing instructions
742 // FP absolute value
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H A DAArch64SchedThunderX2T99.td40 // Port 0: ALU, FP/SIMD.
43 // Port 1: ALU, FP/SIMD, integer mul/div.
63 // "THX2T99I1" for ALU ops on port 1 and "THX2T99F1" for FP ops on port 1.
74 // Crypto FP/SIMD micro-ops only on port 1.
77 // FP/SIMD micro-ops on ports 0 and 1.
589 // 3.10 FP Load Instructions
859 // 3.11 FP Store Instructions
1090 // 3.8 FP Data Processing Instructions
1093 // FP absolute value
1094 // FP mi
[all...]
H A DAArch64SchedNeoverseN2.td44 def N2UnitV0 : ProcResource<1>; // FP/ASIMD 0
45 def N2UnitV1 : ProcResource<1>; // FP/ASIMD 1
47 def N2UnitV : ProcResGroup<[N2UnitV0, N2UnitV1]>; // FP/ASIMD 0/1
821 // FP data processing instructions
824 // FP absolute value
825 // FP arithmetic
826 // FP min/max
827 // FP negate
828 // FP select
831 // FP compare
[all …]
H A DAArch64SchedNeoverseN3.td44 def N3UnitV0 : ProcResource<1>; // FP/ASIMD 0
45 def N3UnitV1 : ProcResource<1>; // FP/ASIMD 1
806 // FP data processing instructions
809 // FP absolute value
810 // FP arithmetic
811 // FP min/max
812 // FP negate
813 // FP select
816 // FP compare
819 // FP divide and square root operations are now performed using
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H A DAArch64SchedExynosM3.td45 def M3PipeF0 : ProcResource<1>; // FP #0
47 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
48 def M3UnitFADD0 : ProcResource<1>; // Simple FP
49 def M3UnitFCVT0 : ProcResource<1>; // FP conversion
50 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized)
52 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea
56 def M3PipeF1 : ProcResource<1>; // FP #1
58 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication
59 def M3UnitFADD1 : ProcResource<1>; // Simple FP
60 def M3UnitFDIV0 : ProcResource<2>; // FP divisio
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H A DAArch64CallingConvention.td264 // The first 4 FP/Vector arguments are passed in XMM registers.
286 // Integer/FP values get stored in stack slots that are 8 bytes in size and
305 // The X86-64 calling convention always returns FP values in XMM0.
542 // FP, LR, and X18
570 // requires the frame-record (LR, FP) to be at the top the callee-save area,
582 X25, X26, X27, X28, LR, FP,
590 // Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
591 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
592 // and not (LR,FP) pairs.
594 X25, X26, X27, X28, FP, LR,
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H A DAArch64SchedNeoverseV2.td50 def V2UnitV0 : ProcResource<1>; // FP/ASIMD 0
51 def V2UnitV1 : ProcResource<1>; // FP/ASIMD 1
52 def V2UnitV2 : ProcResource<1>; // FP/ASIMD 2
53 def V2UnitV3 : ProcResource<1>; // FP/ASIMD 3
65 def V2UnitV : ProcResGroup<[V2UnitV0, V2UnitV1, V2UnitV2, V2UnitV3]>; // FP/ASIMD 0/1/2/3
66 def V2UnitV01 : ProcResGroup<[V2UnitV0, V2UnitV1]>; // FP/ASIMD 0/1
67 def V2UnitV02 : ProcResGroup<[V2UnitV0, V2UnitV2]>; // FP/ASIMD 0/2
68 def V2UnitV13 : ProcResGroup<[V2UnitV1, V2UnitV3]>; // FP/ASIMD 1/3
69 def V2UnitV23 : ProcResGroup<[V2UnitV2, V2UnitV3]>; // FP/ASIMD 2/3
1289 // FP data processing instructions
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H A DAArch64SchedA57.td445 // ASIMD FP arith, normal, D-form
447 // ASIMD FP arith, normal, Q-form
450 // ASIMD FP arith, pairwise, D-form
452 // ASIMD FP arith, pairwise, Q-form
455 // ASIMD FP compare, D-form
457 // ASIMD FP compare, Q-form
460 // ASIMD FP convert, long and narrow
462 // ASIMD FP convert, other, D-form
464 // ASIMD FP convert, other, Q-form
467 // ASIMD FP divid
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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-c64x.pl105 STDW A3:A2,*FP[-7]
205 || LDDW *FP[-9],A$A[3][0]:A$A[4][0] ; restore offloaded data
374 ||[!A0] LDDW *FP[-7],A3:A2
410 || STDW A13:A12,*FP[-4]
412 || STDW A11:A10,*FP[-5]
414 || STW A14,*FP[-6]
524 || LDW *FP[-6],A14
540 || LDDW *FP[-5],A11:A10
542 || LDDW *FP[-4],A13:A12
559 || STDW A13:A12,*FP[-4]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp50 MCRegister FP = TRI->getFrameRegister(MF); in emitPrologue() local
97 .addReg(FP) in emitPrologue()
111 .addReg(FP) in emitPrologue()
112 .addReg(FP); in emitPrologue()
118 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::OR), FP) in emitPrologue()
124 nullptr, MRI->getDwarfRegNum(FP, true), StackSize); in emitPrologue()
196 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::OR), FP) in emitPrologue()
204 nullptr, MRI->getDwarfRegNum(FP, true))); in emitPrologue()
230 MCRegister FP = TRI->getFrameRegister(MF); in emitEpilogue() local
275 BuildMI(MBB, I, DL, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP); in emitEpilogue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DLegacyPassManager.cpp295 FPPassManager *FP = static_cast<FPPassManager *>(PassManagers[N]); in getContainedManager() local
296 return FP; in getContainedManager()
1331 FunctionPass *FP = getContainedPass(Index); in cleanup() local
1332 AnalysisResolver *AR = FP->getResolver(); in cleanup()
1347 FunctionPass *FP = getContainedPass(Index); in dumpPassStructure() local
1348 FP->dumpPassStructure(Offset + 1); in dumpPassStructure()
1349 dumpLastUses(FP, Offset+1); in dumpPassStructure()
1379 FunctionPass *FP = getContainedPass(Index); in runOnFunction() local
1385 "RunPass", [FP]() { return std::string(FP->getPassName()); }); in runOnFunction()
1387 dumpPassInfo(FP, EXECUTION_MSG, ON_FUNCTION_MSG, Name); in runOnFunction()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h43 #define GET_VT_ATTR(Ty, n, sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ argument
184 #define GET_VT_ATTR(Ty, n, sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in isOverloaded() argument
267 #define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in getVectorElementType() argument
281 #define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in getVectorMinNumElements() argument
311 #define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in getSizeInBits() argument
434 #define GET_VT_ATTR(Ty, n, sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in getFloatingPointVT() argument
435 if (FP == 3 && sz == BitWidth) \ in getFloatingPointVT()
444 #define GET_VT_ATTR(Ty, n, sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in getIntegerVT() argument
474 #define GET_VT_ATTR(Ty, n, sz, Any, Int, FP, Vec, Sc, Tup, NF, nElem, EltTy) \ in getRISCVVectorTupleVT() argument
488 #define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ in getRISCVVectorTupleNumFields() argument
/freebsd/sys/arm/arm/
H A Ddb_trace.c85 state->registers[SP], state->registers[FP]); in db_stack_trace_cmd()
89 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
144 state.registers[FP] = ctx->pcb_regs.sf_r11; in db_trace_thread()
164 state.registers[FP] = (uint32_t)__builtin_frame_address(0); in db_trace_self()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiFrameLowering.cpp107 .addReg(Lanai::FP) in emitPrologue()
115 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP) in emitPrologue()
179 .addReg(Lanai::FP) in emitEpilogue()
183 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP) in emitEpilogue()
184 .addReg(Lanai::FP) in emitEpilogue()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp291 static std::string toString(const APFloat &FP) { in toString() argument
293 if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) && in toString()
294 !FP.bitwiseIsEqual( in toString()
295 APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) { in toString()
296 APInt AI = FP.bitcastToAPInt(); in toString()
307 auto Written = FP.convertToHexString( in toString()
/freebsd/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-c64xplus.pl116 || [A2] STDW A13:A12,*FP[-3]
117 [A2] STDW A11:A10,*FP[-4]
251 LDDW *FP[-4],A11:A10 ; ABI says so
252 LDDW *FP[-3],A13:A12
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp195 Reserved.set(Mips::FP); in getReservedRegs()
281 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : in getFrameRegister()
297 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; in canRealignStack() local
306 if (!MF.getRegInfo().canReserveReg(FP)) in canRealignStack()

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