| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXSubtarget.cpp | 88 case ISD::FNEARBYINT: in hasNativeBF16Support()
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| H A D | NVPTXISelLowering.cpp | 892 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 94 DAG_FUNCTION(nearbyint, 1, 1, experimental_constrained_nearbyint, FNEARBYINT)
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| H A D | VPIntrinsics.def | 443 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1036 FNEARBYINT, enumerator
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| H A D | BasicTTIImpl.h | 2343 ISD = ISD::FNEARBYINT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 253 case ISD::FNEARBYINT: return "fnearbyint"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 119 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; in SoftenFloatResult()
1600 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; in ExpandFloatResult()
2846 case ISD::FNEARBYINT: in PromoteFloatResult()
3331 case ISD::FNEARBYINT: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 437 case ISD::FNEARBYINT: in LegalizeOp()
1301 case ISD::FNEARBYINT: in Expand()
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| H A D | LegalizeVectorTypes.cpp | 107 case ISD::FNEARBYINT: in ScalarizeVectorResult()
1229 case ISD::FNEARBYINT: in SplitVectorResult()
4913 case ISD::FNEARBYINT: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4820 case ISD::FNEARBYINT: in ConvertNodeToLibcall()
5794 case ISD::FNEARBYINT: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 6844 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in visitIntrinsicCall()
9493 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) in visitCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 408 setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
549 ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
677 case ISD::FNEARBYINT: in fnegFoldsIntoOpcode()
1442 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
5122 case ISD::FNEARBYINT: // XXX - Should fround be handled? in performFNegCombine()
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| H A D | AMDGPUISelDAGToDAG.cpp | 158 case ISD::FNEARBYINT: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 813 ISD::FFLOOR, ISD::FNEARBYINT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 334 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
878 setOperationAction(ISD::FNEARBYINT, VT, Expand); in PPCTargetLowering()
940 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1039 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in PPCTargetLowering()
1040 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in PPCTargetLowering()
1046 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
1052 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1256 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 397 setOperationAction(ISD::FNEARBYINT, VT, Expand); in addMVEVectorTypes()
884 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
907 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in ARMTargetLowering()
926 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); in ARMTargetLowering()
929 for (ISD::NodeType Op : {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in ARMTargetLowering()
1075 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); in ARMTargetLowering()
1472 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in ARMTargetLowering()
1489 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in ARMTargetLowering()
1517 setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1260 case ISD::FNEARBYINT: in PreprocessISelDAG()
1278 case ISD::FNEARBYINT: Imm = 0xC; break; in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 799 ISD::FNEARBYINT, in AArch64TargetLowering()
853 setOperationPromotedToType(ISD::FNEARBYINT, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
878 setOperationAction(ISD::FNEARBYINT, V8Narrow, Legal); in AArch64TargetLowering()
902 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
1237 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
1403 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1696 setOperationAction(ISD::FNEARBYINT, VT, Custom); in AArch64TargetLowering()
1781 {ISD::FCEIL, ISD::FDIV, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in AArch64TargetLowering()
2298 setOperationAction(ISD::FNEARBYINT, VT, Default); in addTypeForFixedLengthSVE()
7294 case ISD::FNEARBYINT: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 534 ISD::FNEARBYINT, MVT::f16, in RISCVTargetLowering()
579 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in RISCVTargetLowering()
604 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in RISCVTargetLowering()
1022 ISD::FNEARBYINT, in RISCVTargetLowering()
1085 ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT, in RISCVTargetLowering()
1518 ISD::FNEARBYINT}, in RISCVTargetLowering()
3332 case ISD::FNEARBYINT: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
7720 case ISD::FNEARBYINT: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 574 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 141 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 570 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
635 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in SystemZTargetLowering()
678 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 180 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1726 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
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