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Searched refs:FMUL (Results 1 – 25 of 63) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def54 DAG_INSTRUCTION(FMul, 2, 1, experimental_constrained_fmul, FMUL)
108 // constrained FMA or FMUL + FADD intrinsics.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp5418 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
5422 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
5434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
5438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
5441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
5455 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
5459 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
5462 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
5465 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in getLimitedPrecisionExp2()
5468 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); in getLimitedPrecisionExp2()
[all …]
H A DDAGCombiner.cpp1923 case ISD::FMUL: return visitFMUL(N); in visit()
15850 assert(N.getOpcode() == ISD::FMUL); in isContractableFMUL()
15914 if (!matcher.match(N, ISD::FMUL)) in visitFADDForFMACombine()
15961 if (matcher.match(FMul, ISD::FMUL) && FMul.hasOneUse()) { in visitFADDForFMACombine()
16143 if (!matcher.match(N, ISD::FMUL)) in visitFSUBForFMACombine()
16435 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
16582 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
16632 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) { in visitFADD()
16633 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
16643 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP); in visitFADD()
[all …]
H A DSelectionDAGBuilder.h553 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); } in visitFMul()
H A DLegalizeDAG.cpp2463 SDValue ScaleUp0 = DAG.getNode(ISD::FMUL, dl, VT, X, ScaleUpVal); in expandLdexp()
2464 SDValue ScaleUp1 = DAG.getNode(ISD::FMUL, dl, VT, ScaleUp0, ScaleUpVal); in expandLdexp()
2486 SDValue ScaleDown0 = DAG.getNode(ISD::FMUL, dl, VT, X, ScaleDownVal); in expandLdexp()
2487 SDValue ScaleDown1 = DAG.getNode(ISD::FMUL, dl, VT, ScaleDown0, ScaleDownVal); in expandLdexp()
2517 return DAG.getNode(ISD::FMUL, dl, VT, NewX, AsFP); in expandLdexp()
2578 SDValue ScaleUp = DAG.getNode(ISD::FMUL, dl, VT, Val, ScaleUpK); in expandFrexp()
4759 case ISD::FMUL: in ConvertNodeToLibcall()
5431 case ISD::FMUL: in PromoteNode()
H A DSelectionDAGDumper.cpp289 case ISD::FMUL: return "fmul"; in getOperationName()
H A DLegalizeVectorOps.cpp356 case ISD::FMUL: in LegalizeOp()
1661 fHI = DAG.getNode(ISD::FMUL, DL, Node->getValueType(0), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
H A DLegalizeFloatTypes.cpp111 case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break; in SoftenFloatResult()
1441 case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break; in ExpandFloatResult()
2634 case ISD::FMUL: in PromoteFloatResult()
3074 case ISD::FMUL: in SoftPromoteHalfResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp957 { ISD::FMUL, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
958 { ISD::FMUL, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
959 { ISD::FMUL, MVT::v2f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
960 { ISD::FMUL, MVT::f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
972 { ISD::FMUL, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
973 { ISD::FMUL, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
974 { ISD::FMUL, MVT::v4f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
975 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1091 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // mulsd in getArithmeticInstrCost()
1092 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // mulss in getArithmeticInstrCost()
[all …]
H A DX86IntrinsicsInfo.h918 X86_INTRINSIC_DATA(avx512_mul_pd_512, INTR_TYPE_2OP, ISD::FMUL,
920 X86_INTRINSIC_DATA(avx512_mul_ps_512, INTR_TYPE_2OP, ISD::FMUL,
1437 X86_INTRINSIC_DATA(avx512fp16_mul_ph_512, INTR_TYPE_2OP, ISD::FMUL,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp535 ISD::FFLOOR, ISD::FTRUNC, ISD::FMUL, in AMDGPUTargetLowering()
649 case ISD::FMUL: in fnegFoldsIntoOpcode()
1957 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT, in LowerDIVREM24()
2076 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
2078 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64()
2645 SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags); in getScaledLogInput()
2686 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Y, Flags); in getMad()
2737 R = DAG.getNode(ISD::FMUL, DL, VT, Y, C, Flags); in LowerFLOGCommon()
2760 SDValue YTCT = DAG.getNode(ISD::FMUL, DL, VT, YT, CT, Flags); in LowerFLOGCommon()
2820 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, LogSrc, Log2Inv, Flags); in LowerFLOGUnsafe()
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H A DSIISelLowering.cpp209 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV, in SITargetLowering()
779 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FMINNUM_IEEE, in SITargetLowering()
801 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE}, in SITargetLowering()
812 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG}, in SITargetLowering()
814 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA}, in SITargetLowering()
5853 case ISD::FMUL: in LowerOperation()
10494 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags); in lowerFastUnsafeFDIV()
10519 SDValue Ret = DAG.getNode(ISD::FMUL, SL, VT, X, R); in lowerFastUnsafeFDIV64()
10536 case ISD::FMUL: in getFPBinOp()
10580 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1); in LowerFDIV16()
[all …]
H A DAMDGPUTargetTransformInfo.cpp582 case ISD::FMUL: in getArithmeticInstrCost()
H A DR600ISelLowering.cpp693 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
713 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td51 FMUL,
H A DP9InstrResources.td431 FMUL,
483 (instregex "FMUL(S)?_rec$"),
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def114 ADD_BINARY_VVP_OP_COMPACT(FMUL) REGISTER_PACKED(VVP_FMUL)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h399 FMUL, enumerator
H A DSDPatternMatch.h636 return BinaryOpc_match<LHS, RHS, true>(ISD::FMUL, L, R);
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td260 // Special encoding for the FMUL family of instructions.
264 // ff = 0b01 for FMUL
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td603 (instregex "^(FMUL|FMULX)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
608 (instregex "^(FMUL|FMULX)v1i64_indexed$")>;
629 (instregex "^(FMUL|FMULX)(v2f64|v4f32|v4i32_indexed)$")>;
632 (instregex "^(FMUL|FMULX)v2i64_indexed$")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td38 defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>,
H A DMipsSEISelLowering.cpp130 setOperationAction(ISD::FMUL, MVT::f16, Promote); in MipsSETargetLowering()
390 setOperationAction(ISD::FMUL, Ty, Legal); in addMSAFloatType()
1889 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1902 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td126 defm FMUL : FT_XYZ<0b010000, "fmul", BinOpFrag<(fmul node:$LHS, node:$RHS)>>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1897 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1922 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1980 setOperationAction(ISD::FMUL, MVT::f32, Promote); in SparcTargetLowering()
3276 case ISD::FMUL: return LowerF128Op(Op, DAG, in LowerOperation()

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