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Searched refs:FMOV (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredNeoverse.td73 // FMOV Hd, WZR
74 // FMOV Hd, XZR
75 // FMOV Sd, WZR
76 // FMOV Dd, XZR
H A DAArch64SchedOryon.td40 // cross IXU/LSU/VXU resource group for FMOV P41 of VXU
195 // cross IXU/LSU/VXU resource group for FMOV P41 of VXU
1367 def : InstRW<[ORYONWrite_I2V_4Cyc_I45], (instregex "^FMOV[HSD][WX]r", "^FMOVDXHighr")>;
1373 def : InstRW<[ORYONWrite_V2I_3Cyc_FP01], (instregex "^FMOV[WX][HSD]r", "FMOVXDHighr")>;
1379 def : InstRW<[ORYONWrite_V2V_2Cyc_FP0123], (instregex "^FMOV[HSD]r")>;
1380 def : InstRW<[ORYONWrite_V2V_2Cyc_FP0123], (instregex "^FMOV[HSD]i")>;
H A DAArch64SchedExynosM3.td556 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>;
561 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>;
562 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>;
563 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>;
H A DAArch64SchedExynosM5.td724 def : InstRW<[M5WriteNALU1], (instregex "^FMOV[HSD]i")>;
725 def : InstRW<[M5WriteNALU2], (instregex "^FMOV[HSD]r")>;
726 def : InstRW<[M5WriteSA], (instregex "^FMOV[WX][HSD]r")>;
727 def : InstRW<[M5WriteFCVTA], (instregex "^FMOV[HSD][WX]r")>;
H A DAArch64SchedFalkorDetails.td1149 def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>;
1150 def : InstRW<[FalkorWr_1GTOV_0cyc], (instregex "^FMOV(S|D)i$")>; // imm fwd
1153 def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(SW|DX|DXHigh)r$")>;
1154 def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "^FMOV(Sr|Dr|v.*_ns)$")>; // imm fwd
H A DAArch64SchedAmpere1.td929 def : InstRW<[Ampere1Write_5cyc_1BS], (instregex "^FMOV[HSD][WX]r")>;
931 def : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^FMOV[HSD][ri]")>;
933 def : InstRW<[Ampere1Write_4cyc_1Z], (instregex "^FMOV[WX][HSD]r")>;
H A DAArch64SchedAmpere1B.td911 def : InstRW<[Ampere1BWrite_5cyc_1BS], (instregex "^FMOV[HSD][WX]r")>;
913 def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^FMOV[HSD][ri]")>;
915 def : InstRW<[Ampere1BWrite_3cyc_1Z], (instregex "^FMOV[WX][HSD]r")>;
H A DAArch64SchedExynosM4.td667 def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>;
668 def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>;
669 def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>;
H A DAArch64SchedTSV110.td518 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
519 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOV[SD][ir]$")>;
H A DAArch64ISelLowering.h198 FMOV, enumerator
H A DAArch64SchedKryoDetails.td861 (instregex "FMOV(XDHigh|DXHigh|DX)r")>;
867 (instregex "FMOV(Di|Dr|Si|Sr|SWr|WSr|XDr|v.*_ns)")>;
H A DAArch64InstrInfo.td757 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
4872 defm FMOV : UnscaledConversion<"fmov">;
4874 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
4932 defm FMOV : SingleOperandFPDataNoException<0b0000, "fmov">;
5181 defm FMOV : FPMoveImmediate<"fmov">;
7514 // AdvSIMD FMOV
9696 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for the
H A DAArch64ISelLowering.cpp2628 MAKE_CASE(AArch64ISD::FMOV) in getTargetNodeName()
13889 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits))) in ConstantBuildVector()
H A DAArch64InstrFormats.td5182 // Unscaled integer <-> floating point conversion (i.e. FMOV)
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td162 defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
H A DMipsInstrFPU.td593 defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td155 defm FMOV : FT_MOV<0b000100, "fmov">;