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Searched refs:FABS (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h959 FABS, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp394 setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR, in AMDGPUTargetLowering()
530 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, in AMDGPUTargetLowering()
621 ISD::FABS, ISD::AssertZext, in AMDGPUTargetLowering()
1588 if (Val.getOpcode() == ISD::FABS) in peekFPSignOps()
1985 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1988 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
2466 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFROUNDEVEN()
2509 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2616 SDValue Fabs = DAG.getNode(ISD::FABS, SL, VT, Src, Flags); in getIsFinite()
3475 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
[all …]
H A DAMDGPUISelDAGToDAG.cpp146 case ISD::FABS: in fp16SrcZerosHighBits()
2872 if (AllowAbs && Src.getOpcode() == ISD::FABS) { in SelectVOP3ModsImpl()
2918 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
3193 if (El.getOpcode() != ISD::FABS) in selectWMMAModsNegAbs()
3206 assert(ModOpcode == ISD::FABS); in selectWMMAModsNegAbs()
3289 ModOpcode = (ElF16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
3310 ModOpcode = (ElV2f16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
3337 (ElF32.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF32NegAbs()
H A DR600Instructions.td681 class FABS <RegisterClass rc> : AMDGPUShaderInst <
684 "FABS $dst, $src0",
1207 def FABS_R600 : FABS<R600_Reg32>;
H A DSIISelLowering.cpp228 setOperationAction(ISD::FABS, MVT::bf16, Legal); in SITargetLowering()
750 setOperationAction(ISD::FABS, MVT::v2f16, Legal); in SITargetLowering()
820 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v4f16, Custom); in SITargetLowering()
831 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v2f16, Custom); in SITargetLowering()
5827 case ISD::FABS: in LowerOperation()
6450 case ISD::FABS: { in ReplaceNodeResults()
10595 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS, Flags); in lowerFDIV_FAST()
10869 SDValue Fabs = DAG.getNode(ISD::FABS, dl, VT, Val); in LowerFFREXP()
11574 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X || in performAndCombine()
12665 case ISD::FABS: in isCanonicalized()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1797 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1904 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1907 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1926 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2922 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3066 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3282 case ISD::FABS: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
H A DAArch64SchedCyclone.td436 // FABS,FNEG are WriteF
H A DAArch64SchedExynosM3.td537 def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>;
H A DAArch64SchedExynosM4.td633 def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td123 defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
H A DMipsISelLowering.cpp356 setOperationAction(ISD::FABS, MVT::f32, Custom); in MipsTargetLowering()
357 setOperationAction(ISD::FABS, MVT::f64, Custom); in MipsTargetLowering()
1253 case ISD::FABS: return lowerFABS(Op, DAG); in LowerOperation()
H A DMipsInstrFPU.td531 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;
H A DMipsSEISelLowering.cpp135 setOperationAction(ISD::FABS, MVT::f16, Promote); in MipsSETargetLowering()
384 setOperationAction(ISD::FABS, Ty, Legal); in addMSAFloatType()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp72 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
1402 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1541 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
2597 case ISD::FABS: in PromoteFloatResult()
3038 case ISD::FABS: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp195 case ISD::FABS: return "fabs"; in getOperationName()
H A DDAGCombiner.cpp1940 case ISD::FABS: return visitFABS(N); in visit()
15324 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
15332 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
15349 return FPOpcode == ISD::FABS ? TLI.isFAbsFree(VT) : TLI.isFNegFree(VT); in foldBitcastedFPLogic()
15470 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
15486 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
15504 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
17035 TLI.isOperationLegal(ISD::FABS, VT)) { in visitFMUL()
17068 DAG.getNode(ISD::FABS, DL, VT, X)); in visitFMUL()
17070 return DAG.getNode(ISD::FABS, DL, VT, X); in visitFMUL()
[all …]
H A DLegalizeDAG.cpp1647 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) && in ExpandFCOPYSIGN()
1649 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag); in ExpandFCOPYSIGN()
3602 case ISD::FABS: in ExpandNode()
5553 case ISD::FABS: in PromoteNode()
H A DLegalizeVectorOps.cpp393 case ISD::FABS: in LegalizeOp()
H A DSelectionDAG.cpp5432 case ISD::FABS: in isKnownNeverNaN()
5672 return Op.getOpcode() == ISD::FABS; in cannotBeOrderedNegativeFP()
5917 case ISD::FABS: in getNode()
6182 case ISD::FABS: in getNode()
6184 return getNode(ISD::FABS, DL, VT, N1.getOperand(0)); in getNode()
6485 case ISD::FABS: in FoldConstantArithmetic()
H A DTargetLowering.cpp5214 bool IsFabs = N0.getOpcode() == ISD::FABS; in SimplifySetCC()
7230 SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op); in getSqrtInputTest()
8623 isOperationLegalOrCustom(ISD::FABS, OperandVT.getScalarType())) { in expandIS_FPCLASS()
8625 SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op); in expandIS_FPCLASS()
11256 if (isOperationLegalOrCustom(ISD::FABS, OperandVT)) { in expandRoundInexactToOdd()
11257 AbsWide = DAG.getNode(ISD::FABS, dl, OperandVT, Op); in expandRoundInexactToOdd()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td119 defm FABS : FT_XZ<0b000110, "fabs", UnOpFrag<(fabs node:$Src)>>;
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def373 VP_PROPERTY_FUNCTIONAL_SDOPC(FABS)
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrArithmetic.td1062 defm FABS : MxFUnaryOp<"abs", 0b1011000, 0b1011100, 0b0011000>;
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp833 for (const auto &Op : {ISD::FABS}) { in NVPTXTargetLowering()
2570 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A); in LowerFROUND32()
2611 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A); in LowerFROUND64()

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