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Searched refs:ExtVal (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPFixedPoint.h230 APSInt ExtVal =
233 return -((-ExtVal).relativeShl(getLsbWeight()));
234 return ExtVal.relativeShl(getLsbWeight());
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp640 int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue(); in lowerAsmOperandForConstraint() local
641 Ops.push_back(MachineOperand::CreateImm(ExtVal)); in lowerAsmOperandForConstraint()
H A DLegalizerHelper.cpp4270 auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg); in lowerStore() local
4274 auto SmallVal = MIRBuilder.buildLShr(NewSrcTy, ExtVal, ShiftAmt); in lowerStore()
4287 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); in lowerStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h71 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
H A DWebAssemblyISelLowering.cpp1004 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
1005 EVT ExtT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
1006 EVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getValueType(0); in isVectorLoadExtDesirable()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2732 ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); in optimizeCallInst() local
2733 if (!ExtVal || !ExtVal->hasOneUse() || in optimizeCallInst()
2734 ExtVal->getParent() == CI->getParent()) in optimizeCallInst()
2737 ExtVal->moveBefore(CI->getIterator()); in optimizeCallInst()
2740 InsertedInsts.insert(ExtVal); in optimizeCallInst()
4984 Value *ExtVal = SExt; in promoteOperandForTruncAndAnyExt() local
4994 ExtVal = ZExt; in promoteOperandForTruncAndAnyExt()
5007 Instruction *ExtInst = dyn_cast<Instruction>(ExtVal); in promoteOperandForTruncAndAnyExt()
5014 return ExtVal; in promoteOperandForTruncAndAnyExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h485 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
H A DARMISelLowering.cpp19352 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
19353 EVT VT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
19358 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal.getOperand(0))) { in isVectorLoadExtDesirable()
19370 if (ExtVal->use_empty() || in isVectorLoadExtDesirable()
19371 !ExtVal->user_begin()->isOnlyUserOf(ExtVal.getNode())) in isVectorLoadExtDesirable()
19374 SDNode *U = *ExtVal->user_begin(); in isVectorLoadExtDesirable()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h814 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
H A DAArch64ISelLowering.cpp6405 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
6406 EVT ExtVT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
6415 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal->getOperand(0))) { in isVectorLoadExtDesirable()
19546 uint64_t ExtVal = C->getZExtValue(); in performSVEAndCombine() local
19548 auto MaskAndTypeMatch = [ExtVal](EVT VT) -> bool { in performSVEAndCombine()
19549 return ((ExtVal == 0xFF && VT == MVT::i8) || in performSVEAndCombine()
19550 (ExtVal == 0xFFFF && VT == MVT::i16) || in performSVEAndCombine()
19551 (ExtVal == 0xFFFFFFFF && VT == MVT::i32)); in performSVEAndCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2446 SDValue ExtVal = CurDAG->getSignedConstant(Offset, DL, VT); in matchIndexRecursively() local
2447 SDValue ExtAdd = CurDAG->getNode(ISD::ADD, DL, VT, ExtSrc, ExtVal); in matchIndexRecursively()
2449 insertDAGNode(*CurDAG, N, ExtVal); in matchIndexRecursively()
2496 SDValue ExtVal = CurDAG->getConstant(Offset, DL, VT); in matchIndexRecursively() local
2497 SDValue ExtAdd = CurDAG->getNode(SrcOpc, DL, VT, ExtSrc, ExtVal); in matchIndexRecursively()
2499 insertDAGNode(*CurDAG, N, ExtVal); in matchIndexRecursively()
H A DX86ISelLowering.cpp35574 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
35575 if (isa<MaskedLoadSDNode>(ExtVal.getOperand(0))) in isVectorLoadExtDesirable()
35578 EVT SrcVT = ExtVal.getOperand(0).getValueType(); in isVectorLoadExtDesirable()
61436 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue() in LowerAsmOperandForConstraint() local
61438 Result = DAG.getTargetConstant(ExtVal, SDLoc(Op), MVT::i64); in LowerAsmOperandForConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3242 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, V, in LowerSTOREVector() local
3250 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
3251 Ops.push_back(ExtVal); in LowerSTOREVector()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3301 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; } in isVectorLoadExtDesirable() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2141 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, in ExtendToInt64() local
2144 return ExtVal; in ExtendToInt64()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp5790 int64_t ExtVal = in LowerAsmOperandForConstraint() local
5793 DAG.getTargetConstant(Offset + ExtVal, SDLoc(C), MVT::i64)); in LowerAsmOperandForConstraint()
H A DDAGCombiner.cpp15994 SDValue ExtVal = N0.getOperand(1); in visitTRUNCATE() local
15995 EVT ExtVT = cast<VTSDNode>(ExtVal)->getVT(); in visitTRUNCATE()
15998 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, TrX, ExtVal); in visitTRUNCATE()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp7800 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
7804 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()