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Searched refs:ExtVT (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp749 EVT LoadResultTy, EVT &ExtVT);
6418 EVT LoadResultTy, EVT &ExtVT) { in isAndLoadExtLoad() argument
6424 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); in isAndLoadExtLoad()
6427 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
6429 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
6441 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
6445 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
6448 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
6567 EVT ExtVT; in SearchForAndLoads() local
6568 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) && in SearchForAndLoads()
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H A DTargetLowering.cpp2051 EVT ExtVT = EVT::getIntegerVT(*TLO.DAG.getContext(), LowBits); in SimplifyDemandedBits() local
2053 ExtVT = EVT::getVectorVT(*TLO.DAG.getContext(), ExtVT, in SimplifyDemandedBits()
2058 getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) == Legal) in SimplifyDemandedBits()
2062 TLO.DAG.getValueType(ExtVT))); in SimplifyDemandedBits()
9333 EVT ExtVT = VT.getIntegerVT(*DAG.getContext(), 2 * BW); in expandAVG() local
9334 if (isTypeLegal(ExtVT) && isTruncateFree(ExtVT, VT)) { in expandAVG()
9335 LHS = DAG.getNode(ExtOpc, dl, ExtVT, LHS); in expandAVG()
9336 RHS = DAG.getNode(ExtOpc, dl, ExtVT, RHS); in expandAVG()
9337 SDValue Avg = DAG.getNode(ISD::ADD, dl, ExtVT, LHS, RHS); in expandAVG()
9339 Avg = DAG.getNode(ISD::ADD, dl, ExtVT, Avg, in expandAVG()
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H A DLegalizeIntegerTypes.cpp1687 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(), in PromoteIntRes_TRUNCATE() local
1689 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc); in PromoteIntRes_TRUNCATE()
5639 EVT ExtVT = N->getMemoryVT(); in ExpandIntOp_STORE() local
5640 unsigned EBytes = ExtVT.getStoreSize(); in ExpandIntOp_STORE()
5644 ExtVT.getSizeInBits() - ExcessBits); in ExpandIntOp_STORE()
5772 EVT ExtVT = NOutVT.changeVectorElementType(PromEltVT); in PromoteIntRes_EXTRACT_SUBVECTOR() local
5773 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
H A DLegalizeVectorTypes.cpp491 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); in ScalarizeVecRes_InregOp()
494 LHS, DAG.getValueType(ExtVT)); in ScalarizeVecRes_VecInregOp()
5317 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecRes_InregOp()
5323 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); in WidenVecRes_MERGE_VALUES()
5978 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(), in convertMask()
5980 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask); in convertMask()
487 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); ScalarizeVecRes_InregOp() local
5313 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), WidenVecRes_InregOp() local
5974 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(), convertMask() local
H A DSelectionDAG.cpp4630 EVT ExtVT = Ext.getValueType(); in ComputeNumSignBits() local
4634 ExtVT.getScalarSizeInBits() - ExtendeeVT.getScalarSizeInBits(); in ComputeNumSignBits()
12462 EVT ExtVT = cast<VTSDNode>(Operands[1])->getVT().getVectorElementType(); in UnrollVectorOp() local
12465 getValueType(ExtVT))); in UnrollVectorOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp11930 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale), in lowerShuffleAsSpecificZeroOrAnyExtend() local
11935 DL, ExtVT, InputV, DAG); in lowerShuffleAsSpecificZeroOrAnyExtend()
12220 MVT ExtVT = VT; in lowerShuffleAsElementInsertion() local
12265 ExtVT = MVT::getVectorVT(MVT::i32, ExtVT.getSizeInBits() / 32); in lowerShuffleAsElementInsertion()
12275 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerShuffleAsElementInsertion()
12276 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2)); in lowerShuffleAsElementInsertion()
12280 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerShuffleAsElementInsertion()
12291 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!"); in lowerShuffleAsElementInsertion()
12307 return DAG.getNode(MovOpc, DL, ExtVT, V1, V2); in lowerShuffleAsElementInsertion()
12314 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2); in lowerShuffleAsElementInsertion()
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H A DX86ISelLowering.h1063 EVT ExtVT) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp339 EVT ExtVT = TLI.getTypeForExtReturn(Ctx, VT, in lowerReturnVal() local
341 if (ExtVT != VT) { in lowerReturnVal()
342 RetInfo.Ty = ExtVT.getTypeForEVT(Ctx); in lowerReturnVal()
H A DAMDGPUISelLowering.h220 EVT ExtVT) const override;
H A DAMDGPUISelLowering.cpp3916 EVT ExtVT = cast<VTSDNode>(N1)->getVT(); in performAssertSZExtCombine() local
3921 if (SrcVT.bitsGE(ExtVT)) { in performAssertSZExtCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2513 MVT ExtVT; in performVectorExtendToFPCombine() local
2515 ExtVT = MVT::v4i32; in performVectorExtendToFPCombine()
2517 ExtVT = MVT::v2i32; in performVectorExtendToFPCombine()
2523 SDValue Conv = DAG.getNode(Op, SDLoc(N), ExtVT, N->getOperand(0)); in performVectorExtendToFPCombine()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DNumericalStabilitySanitizer.cpp1874 Type *ExtVT = Config.getExtendedFPType(BitcastTy); in propagateNonFTStore() local
1876 Builder.CreateFPExt(Builder.CreateBitCast(C, BitcastTy), ExtVT); in propagateNonFTStore()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1101 EVT ExtVT = EVT::getEVT(Dst);
1106 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
H A DTargetLowering.h923 virtual bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const { in preferSextInRegOfTruncate() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8136 EVT ExtVT = VT.getVectorElementType(); in LowerBUILD_VECTOR() local
8137 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElts / 2); in LowerBUILD_VECTOR()
9396 EVT ExtVT = ToVT.getHalfNumVectorElementsVT(*DAG.getContext()); in LowerVectorExtend() local
9398 ExtVT = MVT::v8i16; in LowerVectorExtend()
9402 SDValue Ext = DAG.getNode(Opcode, DL, DAG.getVTList(ExtVT, ExtVT), Op); in LowerVectorExtend()
18016 MVT ExtVT, HalfVT; in PerformMinMaxCombine() local
18019 ExtVT = MVT::v4i16; in PerformMinMaxCombine()
18022 ExtVT = MVT::v8i8; in PerformMinMaxCombine()
18033 DAG.getValueType(ExtVT)); in PerformMinMaxCombine()
18784 EVT ExtVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT( in PerformMVEExtCombine() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4423 MVT ExtVT = in LowerVectorFP_TO_INT() local
4427 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {ExtVT, MVT::Other}, in LowerVectorFP_TO_INT()
4432 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); in LowerVectorFP_TO_INT()
6111 EVT ExtVT = ExtVal.getValueType(); in isVectorLoadExtDesirable() local
6112 if (!ExtVT.isScalableVector() && !Subtarget->useSVEForFixedLengthVectors()) in isVectorLoadExtDesirable()
6121 if (!isLoadExtLegalOrCustom(ISD::ZEXTLOAD, ExtVT, Ld->getValueType(0))) { in isVectorLoadExtDesirable()
6124 if (!ExtVT.isScalableVector()) in isVectorLoadExtDesirable()
20264 EVT ExtVT = VecToExtend.getValueType().changeVectorElementType(MVT::i32); in performBuildVectorCombine() local
20265 if (!DAG.getTargetLoweringInfo().isTypeLegal(ExtVT)) in performBuildVectorCombine()
20270 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, DL, ExtVT, VecToExtend); in performBuildVectorCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6597 EVT ExtVT = Op.getValueType(); in combineExtract() local
6599 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize(); in combineExtract()
7460 EVT ExtVT = EVT::getVectorVT( in combineINT_TO_FP() local
7464 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8753 EVT ExtVT = Src.getValueType(); in LowerINT_TO_FPVector() local
8755 ExtVT = EVT::getVectorVT(*DAG.getContext(), WideVT.getVectorElementType(), in LowerINT_TO_FPVector()
8759 DAG.getValueType(ExtVT)); in LowerINT_TO_FPVector()
14880 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), in addShuffleForVecExtend() local
14884 DAG.getValueType(ExtVT)); in addShuffleForVecExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8151 MVT ExtVT = Op.getSimpleValueType(); in lowerFixedLengthVectorExtendToRVV()
8153 if (!ExtVT.isFixedLengthVector()) in lowerFixedLengthVectorExtendToRVV()
8159 MVT ContainerExtVT = getContainerForFixedLengthVector(ExtVT); in lowerFixedLengthVectorExtendToRVV()
8173 return convertFromScalableVector(ExtVT, Ext, DAG, Subtarget);
8149 MVT ExtVT = Op.getSimpleValueType(); lowerFixedLengthVectorExtendToRVV() local