Lines Matching refs:ExtVT
11930 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale), in lowerShuffleAsSpecificZeroOrAnyExtend() local
11935 DL, ExtVT, InputV, DAG); in lowerShuffleAsSpecificZeroOrAnyExtend()
12220 MVT ExtVT = VT; in lowerShuffleAsElementInsertion() local
12265 ExtVT = MVT::getVectorVT(MVT::i32, ExtVT.getSizeInBits() / 32); in lowerShuffleAsElementInsertion()
12275 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerShuffleAsElementInsertion()
12276 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2)); in lowerShuffleAsElementInsertion()
12280 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerShuffleAsElementInsertion()
12291 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!"); in lowerShuffleAsElementInsertion()
12307 return DAG.getNode(MovOpc, DL, ExtVT, V1, V2); in lowerShuffleAsElementInsertion()
12314 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2); in lowerShuffleAsElementInsertion()
12315 if (ExtVT != VT) in lowerShuffleAsElementInsertion()
17438 MVT ExtVT; in lower1BitShuffle() local
17443 ExtVT = MVT::v2i64; in lower1BitShuffle()
17446 ExtVT = MVT::v4i32; in lower1BitShuffle()
17451 ExtVT = Subtarget.hasVLX() ? MVT::v8i32 : MVT::v8i64; in lower1BitShuffle()
17456 ExtVT = Subtarget.canExtendTo512DQ() ? MVT::v16i32 : MVT::v16i16; in lower1BitShuffle()
17462 ExtVT = Subtarget.canExtendTo512BW() ? MVT::v32i16 : MVT::v32i8; in lower1BitShuffle()
17469 ExtVT = MVT::v64i8; in lower1BitShuffle()
17473 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1); in lower1BitShuffle()
17474 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2); in lower1BitShuffle()
17476 SDValue Shuffle = DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask); in lower1BitShuffle()
17481 return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, ExtVT), in lower1BitShuffle()
20243 MVT ExtVT = VT; in LowerZERO_EXTEND_Mask() local
20249 ExtVT = MVT::getVectorVT(MVT::i32, NumElts); in LowerZERO_EXTEND_Mask()
20253 MVT WideVT = ExtVT; in LowerZERO_EXTEND_Mask()
20254 if (!ExtVT.is512BitVector() && !Subtarget.hasVLX()) { in LowerZERO_EXTEND_Mask()
20255 NumElts *= 512 / ExtVT.getSizeInBits(); in LowerZERO_EXTEND_Mask()
20259 WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(), in LowerZERO_EXTEND_Mask()
20269 if (VT != ExtVT) { in LowerZERO_EXTEND_Mask()
20633 MVT ExtVT = MVT::getVectorVT(MVT::i16, InVT.getSizeInBits()/16); in LowerTruncateVecI1() local
20634 In = DAG.getNode(ISD::SHL, DL, ExtVT, in LowerTruncateVecI1()
20635 DAG.getBitcast(ExtVT, In), in LowerTruncateVecI1()
20636 DAG.getConstant(ShiftInx, DL, ExtVT)); in LowerTruncateVecI1()
20679 MVT ExtVT = MVT::getVectorVT(EltVT, NumElts); in LowerTruncateVecI1() local
20680 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In); in LowerTruncateVecI1()
20681 InVT = ExtVT; in LowerTruncateVecI1()
24363 MVT ExtVT = VT; in LowerSIGN_EXTEND_Mask() local
24369 ExtVT = MVT::getVectorVT(MVT::i32, NumElts); in LowerSIGN_EXTEND_Mask()
24373 MVT WideVT = ExtVT; in LowerSIGN_EXTEND_Mask()
24374 if (!ExtVT.is512BitVector() && !Subtarget.hasVLX()) { in LowerSIGN_EXTEND_Mask()
24375 NumElts *= 512 / ExtVT.getSizeInBits(); in LowerSIGN_EXTEND_Mask()
24379 WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(), NumElts); in LowerSIGN_EXTEND_Mask()
24394 if (VT != ExtVT) { in LowerSIGN_EXTEND_Mask()
29365 MVT ExtVT = MVT::getVectorVT(MVT::i16, NumElts / 2); in LowerShiftByScalarVariable() local
29366 if (supportedVectorShiftWithBaseAmnt(ExtVT, Subtarget, Opcode)) { in LowerShiftByScalarVariable()
29372 SDValue BitMask = DAG.getConstant(-1, dl, ExtVT); in LowerShiftByScalarVariable()
29373 BitMask = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, BitMask, in LowerShiftByScalarVariable()
29376 BitMask = getTargetVShiftByConstNode(LogicalX86Op, dl, ExtVT, BitMask, in LowerShiftByScalarVariable()
29382 SDValue Res = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, in LowerShiftByScalarVariable()
29383 DAG.getBitcast(ExtVT, R), BaseShAmt, in LowerShiftByScalarVariable()
29391 SDValue SignMask = DAG.getConstant(0x8080, dl, ExtVT); in LowerShiftByScalarVariable()
29393 getTargetVShiftNode(LogicalX86Op, dl, ExtVT, SignMask, BaseShAmt, in LowerShiftByScalarVariable()
29690 MVT ExtVT = MVT::getVectorVT(EvtSVT, VT.getVectorNumElements()); in LowerShift() local
29692 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
29693 Amt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Amt); in LowerShift()
29695 DAG.getNode(Opc, dl, ExtVT, R, Amt)); in LowerShift()
29750 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2); in LowerShift() local
29784 Amt = DAG.getBitcast(ExtVT, Amt); in LowerShift()
29785 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExtVT, Amt, 5, DAG); in LowerShift()
29817 ALo = DAG.getBitcast(ExtVT, ALo); in LowerShift()
29818 AHi = DAG.getBitcast(ExtVT, AHi); in LowerShift()
29819 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift()
29820 RHi = DAG.getBitcast(ExtVT, RHi); in LowerShift()
29823 SDValue MLo = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RLo, 4, DAG); in LowerShift()
29824 SDValue MHi = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RHi, 4, DAG); in LowerShift()
29825 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
29826 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift()
29829 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo); in LowerShift()
29830 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi); in LowerShift()
29833 MLo = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RLo, 2, DAG); in LowerShift()
29834 MHi = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RHi, 2, DAG); in LowerShift()
29835 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
29836 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift()
29839 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo); in LowerShift()
29840 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi); in LowerShift()
29843 MLo = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RLo, 1, DAG); in LowerShift()
29844 MHi = getTargetVShiftByConstNode(X86OpcI, dl, ExtVT, RHi, 1, DAG); in LowerShift()
29845 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
29846 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift()
29850 RLo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RLo, 8, DAG); in LowerShift()
29851 RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RHi, 8, DAG); in LowerShift()
29857 MVT ExtVT = MVT::v8i32; in LowerShift() local
29863 ALo = DAG.getBitcast(ExtVT, ALo); in LowerShift()
29864 AHi = DAG.getBitcast(ExtVT, AHi); in LowerShift()
29865 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift()
29866 RHi = DAG.getBitcast(ExtVT, RHi); in LowerShift()
29867 SDValue Lo = DAG.getNode(Opc, dl, ExtVT, RLo, ALo); in LowerShift()
29868 SDValue Hi = DAG.getNode(Opc, dl, ExtVT, RHi, AHi); in LowerShift()
29869 Lo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Lo, 16, DAG); in LowerShift()
29870 Hi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Hi, 16, DAG); in LowerShift()
29884 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2); in LowerShift() local
29885 V0 = DAG.getBitcast(ExtVT, V0); in LowerShift()
29886 V1 = DAG.getBitcast(ExtVT, V1); in LowerShift()
29887 Sel = DAG.getBitcast(ExtVT, Sel); in LowerShift()
29889 VT, DAG.getNode(X86ISD::BLENDV, dl, ExtVT, Sel, V0, V1)); in LowerShift()
30035 MVT ExtVT = MVT::getVectorVT(ExtSVT, NumElts / 2); in LowerFunnelShift() local
30049 if (supportedVectorShiftWithBaseAmnt(ExtVT, Subtarget, ShiftOpc)) { in LowerFunnelShift()
30056 SDValue Lo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, Op1, Op0)); in LowerFunnelShift()
30057 SDValue Hi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, Op1, Op0)); in LowerFunnelShift()
30058 Lo = getTargetVShiftNode(ShiftOpc, DL, ExtVT, Lo, ScalarAmt, in LowerFunnelShift()
30060 Hi = getTargetVShiftNode(ShiftOpc, DL, ExtVT, Hi, ScalarAmt, in LowerFunnelShift()
30094 supportedVectorVarShift(ExtVT, Subtarget, ShiftOpc)) { in LowerFunnelShift()
30096 SDValue RLo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, Op1, Op0)); in LowerFunnelShift()
30097 SDValue RHi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, Op1, Op0)); in LowerFunnelShift()
30098 SDValue ALo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, AmtMod, Z)); in LowerFunnelShift()
30099 SDValue AHi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, AmtMod, Z)); in LowerFunnelShift()
30100 SDValue Lo = DAG.getNode(ShiftOpc, DL, ExtVT, RLo, ALo); in LowerFunnelShift()
30101 SDValue Hi = DAG.getNode(ShiftOpc, DL, ExtVT, RHi, AHi); in LowerFunnelShift()
30264 MVT ExtVT = MVT::getVectorVT(ExtSVT, NumElts / 2); in LowerRotate() local
30280 SDValue Lo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, R, R)); in LowerRotate()
30281 SDValue Hi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, R, R)); in LowerRotate()
30282 Lo = getTargetVShiftNode(ShiftX86Opc, DL, ExtVT, Lo, BaseRotAmt, in LowerRotate()
30284 Hi = getTargetVShiftNode(ShiftX86Opc, DL, ExtVT, Hi, BaseRotAmt, in LowerRotate()
30299 (ConstantAmt || supportedVectorVarShift(ExtVT, Subtarget, ShiftOpc))) { in LowerRotate()
30300 SDValue RLo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, R, R)); in LowerRotate()
30301 SDValue RHi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, R, R)); in LowerRotate()
30302 SDValue ALo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, AmtMod, Z)); in LowerRotate()
30303 SDValue AHi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, AmtMod, Z)); in LowerRotate()
30304 SDValue Lo = DAG.getNode(ShiftOpc, DL, ExtVT, RLo, ALo); in LowerRotate()
30305 SDValue Hi = DAG.getNode(ShiftOpc, DL, ExtVT, RHi, AHi); in LowerRotate()
30367 Amt = DAG.getBitcast(ExtVT, Amt); in LowerRotate()
30368 Amt = DAG.getNode(ISD::SHL, DL, ExtVT, Amt, DAG.getConstant(5, DL, ExtVT)); in LowerRotate()
33649 EVT ExtVT = VecOp.getValueType().changeVectorElementTypeToInteger(); in ReplaceNodeResults() local
33650 SDValue Split = DAG.getBitcast(ExtVT, N->getOperand(0)); in ReplaceNodeResults()
37046 EVT ExtVT = EVT::getVectorVT(*TLO.DAG.getContext(), ExtSVT, in targetShrinkDemandedConstant() local
37050 Op.getOperand(1), TLO.DAG.getValueType(ExtVT)); in targetShrinkDemandedConstant()
42544 MVT ExtVT = VT.getSimpleVT(); in SimplifyDemandedVectorEltsForTargetNode() local
42545 ExtVT = MVT::getVectorVT(ExtVT.getScalarType(), in SimplifyDemandedVectorEltsForTargetNode()
42546 ExtSizeInBits / ExtVT.getScalarSizeInBits()); in SimplifyDemandedVectorEltsForTargetNode()
42547 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode()
47783 EVT ExtVT = VT.changeVectorElementType(MVT::i16); in combineMulToPMADDWD() local
47784 Src = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, Src); in combineMulToPMADDWD()
52598 EVT ExtVT = Ext.getValueType(); in detectPMADDUBSW() local
52599 if (ExtVT.getVectorNumElements() != NumElems * 2) { in detectPMADDUBSW()
57947 EVT ExtVT) const { in preferSextInRegOfTruncate()