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Searched refs:EFLAGS (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCMovSetCC.td22 … t.RegClass:$src2, timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
28 … (t.LoadNode addr:$src2), timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
38 (X86cmov 0, t.RegClass:$src1, timm:$cond, EFLAGS))]>, UseEFLAGS, NF;
93 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
95 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
97 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
102 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
104 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
106 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
110 def : Pat<(X86cmov GR16:$src1, 0, timm:$cond, EFLAGS),
[all …]
H A DX86InstrConditionalCompare.td18 let Uses = [EFLAGS];
19 let Defs = [EFLAGS];
81 def : Pat<(X86ccmp GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond, EFLAGS),
83 def : Pat<(X86ccmp GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond, EFLAGS),
85 def : Pat<(X86ccmp GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond, EFLAGS),
87 def : Pat<(X86ccmp GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond, EFLAGS),
90 def : Pat<(X86ccmp GR8:$src1, (i8 imm:$src2), timm:$dcf, timm:$cond, EFLAGS),
92 def : Pat<(X86ccmp GR16:$src1, (i16 imm:$src2), timm:$dcf, timm:$cond, EFLAGS),
94 def : Pat<(X86ccmp GR32:$src1, (i32 imm:$src2), timm:$dcf, timm:$cond, EFLAGS),
96 def : Pat<(X86ccmp GR64:$src1, i64immSExt32_su:$src2, timm:$dcf, timm:$cond, EFLAGS),
[all …]
H A DX86InstrKL.td25 [(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
30 [(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
35 [(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
40 [(set VR128:$dst, EFLAGS, (X86aesdec256kl VR128:$src1, addr:$src2))]>,
45 let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
52 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
55 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
58 let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
71 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in {
H A DX86InstrSNP.td19 let Uses = [RAX], Defs = [EAX, EFLAGS] in
24 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in
28 let Uses = [EAX, ECX, EDX], Defs = [EAX, EFLAGS] in
33 let Uses = [RAX, RCX], Defs = [EAX, EFLAGS] in
38 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in
43 let Uses = [RAX, RDX], Defs = [RAX, RCX, RDX, EFLAGS] in
H A DX86InstrArithmetic.td74 let Defs = [AL, EFLAGS, AX], Uses = [AL] in
76 [(set AL, (node AL, GR8:$src1)), (implicit EFLAGS)]>;
77 let Defs = [AX, DX, EFLAGS], Uses = [AX] in
79 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX] in
81 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX] in
83 let Defs = [AL, EFLAGS, AX], Uses = [AL] in
85 [(set AL, (node AL, (loadi8 addr:$src1))), (implicit EFLAGS)]>;
86 let Defs = [AX, DX, EFLAGS], Uses = [AX] in
88 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX] in
90 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX] in
[all …]
H A DX86FlagsCopyLowering.cpp244 MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in getClobberType()
267 if (none_of(MRI->def_instructions(X86::EFLAGS), [](const MachineInstr &MI) { in runOnMachineFunction()
296 MI.getOperand(0).getReg() == X86::EFLAGS) in runOnMachineFunction()
362 Clobber->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr) in runOnMachineFunction()
370 BI->addLiveIn(X86::EFLAGS); in runOnMachineFunction()
432 assert(DOp.getReg() == X86::EFLAGS && "Unexpected copy def register!"); in runOnMachineFunction()
461 MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in runOnMachineFunction()
487 while (TestMBB->isLiveIn(X86::EFLAGS) && !TestMBB->pred_empty() && in runOnMachineFunction()
519 return MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in runOnMachineFunction()
582 MI.findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr); in runOnMachineFunction()
[all …]
H A DX86InstrMisc.td130 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
135 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
141 let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
148 let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
210 let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
213 let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
250 let Defs = [EFLAGS] in {
253 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>,
257 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>,
261 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>,
[all …]
H A DX86InstrCompiler.td38 // sub / add which can clobber EFLAGS.
39 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
56 // sub / add which can clobber EFLAGS.
57 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
72 let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in {
78 (implicit EFLAGS)]>;
81 let usesCustomInserter = 1, Defs = [EFLAGS] in {
84 let Defs = [EFLAGS] in {
91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
[all …]
H A DX86InstrUtils.td90 class DefEFLAGS { list<Register> Defs = [EFLAGS]; }
91 class UseEFLAGS { list<Register> Uses = [EFLAGS]; }
979 // BinOpRR_F - Instructions that read "reg, reg" and write EFLAGS only.
982 [(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
998 // BinOpRR_RF - Instructions that read "reg, reg", and write "reg", EFLAGS.
1002 [(set t.RegClass:$dst, EFLAGS,
1010 // EFLAGS.
1013 [(set t.RegClass:$dst, EFLAGS,
1015 EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<ndd> {
1031 // BinOpRM_F - Instructions that read "reg, [mem]" and write EFLAGS only.
[all …]
H A DX86SpeculativeLoadHardening.cpp486 ZeroI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in runOnMachineFunction()
736 bool LiveEFLAGS = Succ.isLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
738 CheckingMBB.addLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
765 CMovI->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr) in tracePredStateThroughCFG()
1076 assert(!MBB.isLiveIn(X86::EFLAGS) && in tracePredStateThroughIndirectBranches()
1188 CMovI->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr) in tracePredStateThroughIndirectBranches()
1207 MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)) { in isEFLAGSDefLive()
1219 MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)) { in isEFLAGSLive()
1229 if (MI.killsRegister(X86::EFLAGS, &TRI)) in isEFLAGSLive()
1235 return MBB.isLiveIn(X86::EFLAGS); in isEFLAGSLive()
[all …]
H A DX86CmovConversion.cpp358 if (I.definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) { in collectCmovCandidates()
585 if (MI->killsRegister(X86::EFLAGS, /*TRI=*/nullptr)) in checkEFLAGSLive()
595 if (I->readsRegister(X86::EFLAGS, /*TRI=*/nullptr)) in checkEFLAGSLive()
597 if (I->definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) in checkEFLAGSLive()
603 if (Succ->isLiveIn(X86::EFLAGS)) in checkEFLAGSLive()
696 FalseMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
697 SinkMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
H A DX86FixupSetCC.cpp79 if (MI.definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) in runOnMachineFunction()
105 if (FlagsDefMI->readsRegister(X86::EFLAGS, /*TRI=*/nullptr)) in runOnMachineFunction()
H A DX86InstrTSX.td42 let Defs = [EFLAGS] in
44 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>;
H A DX86InstrFPStack.td16 // Clobbers EFLAGS due to OR instruction used internally.
18 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in {
339 cc, EFLAGS))]>;
343 cc, EFLAGS))]>;
347 cc, EFLAGS))]>,
352 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
361 } // Uses = [EFLAGS], Constraints = "$src1 = $dst"
569 let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
571 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
574 [(set EFLAGS, (X86any_fcm
[all...]
H A DX86FixupLEAs.cpp435 if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI)) in searchALUInst()
529 NewMI1->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
534 NewMI2->addRegisterDead(X86::EFLAGS, TRI); in optLEAALU()
561 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) != in optTwoAddrLEA()
701 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstructionForSlowLEA()
753 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstrForSlow3OpLEA()
H A DX86InstrControl.td73 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
78 [(X86brcond bb:$dst, timm:$cond, EFLAGS)]>;
297 // rather than barriers, and they use EFLAGS.
300 let Uses = [ESP, EFLAGS, SSP] in {
421 // rather than barriers, and they use EFLAGS.
424 let Uses = [RSP, EFLAGS, SSP] in {
H A DX86InstrShiftRotate.td106 let Uses = !listconcat([CL], uses), Defs = [EFLAGS] in {
232 defm RCL: ShiftRotate<"rcl", MRM2r, MRM2m, null_frag, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd, [EFLAGS]>;
233 defm RCR: ShiftRotate<"rcr", MRM3r, MRM3m, null_frag, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd, [EFLAGS]>;
508 Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteSHDrri],
603 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
H A DX86InstrSystem.td47 let Uses = [EFLAGS] in
73 let hasSideEffects = 1, Defs = [RSP, EFLAGS] in {
78 } // hasSideEffects = 1, Defs = [RSP, EFLAGS]
232 let Defs = [EFLAGS] in {
385 let Defs = [EFLAGS] in {
392 } // Defs EFLAGS
452 let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
760 let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
780 // IF (inside EFLAGS) management instructions.
781 let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
[all …]
H A DX86LoadValueInjectionRetHardening.cpp100 ->addRegisterDead(X86::EFLAGS, TRI); in runOnMachineFunction()
H A DX86InstrTBM.td16 let Predicates = [HasTBM], Defs = [EFLAGS] in {
75 } // HasTBM, EFLAGS
H A DX86InstrFragments.td18 // RES = op PTR, PASSTHRU, COND, EFLAGS
22 // op VAL, PTR, COND, EFLAGS
31 // Unary and binary operator instructions that set EFLAGS as a side-effect.
41 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
633 node:$cond, EFLAGS)>;
H A DX86InstrInfo.cpp977 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI); in reMaterialize()
978 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) != in reMaterialize()
1013 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS && in hasLiveCondCodeDef()
1129 if (Instr.modifiesRegister(X86::EFLAGS, TRI)) in findRedundantFlagInstr()
3812 if (I->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->isUndef()) in analyzeBranchImpl()
3972 if (MI.modifiesRegister(X86::EFLAGS, TRI)) { in analyzeBranchPredicate()
3977 if (MI.readsRegister(X86::EFLAGS, TRI)) in analyzeBranchPredicate()
3986 if (Succ->isLiveIn(X86::EFLAGS)) in analyzeBranchPredicate()
4311 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) { in copyPhysReg()
5322 if (Inst.modifiesRegister(X86::EFLAGS, TRI)) { in optimizeCompareInstr()
[all …]
H A DX86CompressEVEX.cpp246 MI.registerDefIsDead(X86::EFLAGS, /*TRI=*/nullptr)) in CompressEVEXImpl()
/freebsd/share/mk/
H A Dbsd.suffixes.mk41 ${FC} ${RFLAGS} ${EFLAGS} ${FFLAGS} ${LDFLAGS} ${.IMPSRC} ${LDLIBS} \
45 ${FC} ${RFLAGS} ${EFLAGS} ${FFLAGS} -c ${.IMPSRC} -o ${.TARGET}
86 ${FC} ${EFLAGS} ${RFLAGS} ${FFLAGS} ${LDFLAGS} ${.IMPSRC} \
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrFormats.td20 // the "EFLAGS" register.
22 // we do not need to add `let Defs/Uses = [EFLAGS]`.

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