Lines Matching refs:EFLAGS

22 …                                     t.RegClass:$src2, timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
28 …                              (t.LoadNode addr:$src2), timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
38                  (X86cmov 0, t.RegClass:$src1, timm:$cond, EFLAGS))]>, UseEFLAGS, NF;
93   def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
95   def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
97   def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
102   def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
104   def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
106   def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
110   def : Pat<(X86cmov GR16:$src1, 0, timm:$cond, EFLAGS),
112   def : Pat<(X86cmov GR32:$src1, 0, timm:$cond, EFLAGS),
114   def : Pat<(X86cmov GR64:$src1, 0, timm:$cond, EFLAGS),
117   def : Pat<(X86cload addr:$src1, 0, timm:$cond, EFLAGS),
119   def : Pat<(X86cload addr:$src1, 0, timm:$cond, EFLAGS),
121   def : Pat<(X86cload addr:$src1, 0, timm:$cond, EFLAGS),
124   def : Pat<(X86cload addr:$src2, GR16:$src1, timm:$cond, EFLAGS),
126   def : Pat<(X86cload addr:$src2, GR32:$src1, timm:$cond, EFLAGS),
128   def : Pat<(X86cload addr:$src2, GR64:$src1, timm:$cond, EFLAGS),
131   def : Pat<(X86cstore GR16:$src2, addr:$src1, timm:$cond, EFLAGS),
133   def : Pat<(X86cstore GR32:$src2, addr:$src1, timm:$cond, EFLAGS),
135   def : Pat<(X86cstore GR64:$src2, addr:$src1, timm:$cond, EFLAGS),
140 let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
143                 [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
147                 [(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
149 } // Uses = [EFLAGS]
152 let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
173 let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {