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Searched refs:DwarfRegNum (Results 1 – 25 of 35) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td129 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
131 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
132 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
133 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
137 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
138 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
139 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
140 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
141 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
142 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td52 def R0 : CSKYReg<0, "r0", ["a0"]>, DwarfRegNum<[0]>;
53 def R1 : CSKYReg<1, "r1", ["a1"]>, DwarfRegNum<[1]>;
54 def R2 : CSKYReg<2, "r2", ["a2"]>, DwarfRegNum<[2]>;
55 def R3 : CSKYReg<3, "r3", ["a3"]>, DwarfRegNum<[3]>;
56 def R4 : CSKYReg<4, "r4", ["l0"]>, DwarfRegNum<[4]>;
57 def R5 : CSKYReg<5, "r5", ["l1"]>, DwarfRegNum<[5]>;
58 def R6 : CSKYReg<6, "r6", ["l2"]>, DwarfRegNum<[6]>;
59 def R7 : CSKYReg<7, "r7", ["l3"]>, DwarfRegNum<[7]>;
60 def R8 : CSKYReg<8, "r8", ["l4"]>, DwarfRegNum<[8]>;
61 def R9 : CSKYReg<9, "r9", ["l5"]>, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td60 def R0 : LoongArchReg<0, "r0", ["zero"]>, DwarfRegNum<[0]>;
61 def R1 : LoongArchReg<1, "r1", ["ra"]>, DwarfRegNum<[1]>;
62 def R2 : LoongArchReg<2, "r2", ["tp"]>, DwarfRegNum<[2]>;
63 def R3 : LoongArchReg<3, "r3", ["sp"]>, DwarfRegNum<[3]>;
64 def R4 : LoongArchReg<4, "r4", ["a0"]>, DwarfRegNum<[4]>;
65 def R5 : LoongArchReg<5, "r5", ["a1"]>, DwarfRegNum<[5]>;
66 def R6 : LoongArchReg<6, "r6", ["a2"]>, DwarfRegNum<[6]>;
67 def R7 : LoongArchReg<7, "r7", ["a3"]>, DwarfRegNum<[7]>;
68 def R8 : LoongArchReg<8, "r8", ["a4"]>, DwarfRegNum<[8]>;
69 def R9 : LoongArchReg<9, "r9", ["a5"]>, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td35 def PCB : MSP430Reg<0, "r0", ["pc"]>, DwarfRegNum<[16]>;
36 def SPB : MSP430Reg<1, "r1", ["sp"]>, DwarfRegNum<[17]>;
37 def SRB : MSP430Reg<2, "r2", ["sr"]>, DwarfRegNum<[18]>;
38 def CGB : MSP430Reg<3, "r3", ["cg"]>, DwarfRegNum<[19]>;
39 def R4B : MSP430Reg<4, "r4", ["fp"]>, DwarfRegNum<[20]>;
40 def R5B : MSP430Reg<5, "r5">, DwarfRegNum<[21]>;
41 def R6B : MSP430Reg<6, "r6">, DwarfRegNum<[22]>;
42 def R7B : MSP430Reg<7, "r7">, DwarfRegNum<[23]>;
43 def R8B : MSP430Reg<8, "r8">, DwarfRegNum<[24]>;
44 def R9B : MSP430Reg<9, "r9">, DwarfRegNum<[25]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td36 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
37 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
38 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
39 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
40 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
41 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
42 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
43 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
44 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
45 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td74 def Y : SparcCtrlReg<0, "y">, DwarfRegNum<[64]>;
140 def G0 : Ri< 0, "g0">, DwarfRegNum<[0]> {
143 def G1 : Ri< 1, "g1">, DwarfRegNum<[1]>;
144 def G2 : Ri< 2, "g2">, DwarfRegNum<[2]>;
145 def G3 : Ri< 3, "g3">, DwarfRegNum<[3]>;
146 def G4 : Ri< 4, "g4">, DwarfRegNum<[4]>;
147 def G5 : Ri< 5, "g5">, DwarfRegNum<[5]>;
148 def G6 : Ri< 6, "g6">, DwarfRegNum<[6]>;
149 def G7 : Ri< 7, "g7">, DwarfRegNum<[7]>;
150 def O0 : Ri< 8, "o0">, DwarfRegNum<[
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
26 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
27 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
34 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaRegisterInfo.td35 def A0 : ARReg<0, "a0">, DwarfRegNum<[0]>;
38 def SP : ARReg<1, "a1", ["sp"]>, DwarfRegNum<[1]>;
41 def A2 : ARReg<2, "a2">, DwarfRegNum<[2]>;
42 def A3 : ARReg<3, "a3">, DwarfRegNum<[3]>;
43 def A4 : ARReg<4, "a4">, DwarfRegNum<[4]>;
44 def A5 : ARReg<5, "a5">, DwarfRegNum<[5]>;
45 def A6 : ARReg<6, "a6">, DwarfRegNum<[6]>;
46 def A7 : ARReg<7, "a7">, DwarfRegNum<[7]>;
49 def A8 : ARReg<8, "a8">, DwarfRegNum<[8]>;
51 def A9 : ARReg<9, "a9">, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td235 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
236 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
237 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
238 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
239 def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
240 def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
241 def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
242 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
243 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
281 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td86 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
88 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
89 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
90 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
91 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
92 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
93 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
94 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
96 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
97 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td31 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
35 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
39 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
44 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
46 def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
47 def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>;
48 def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>;
49 def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>;
50 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;
51 def BLINK : Core<31, "%blink">, DwarfRegNum<[31]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoMMA.td36 def SPEACC: DwarfRegNum<[99, 111]>;
39 def ACC0 : ACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>;
40 def ACC1 : ACC<1, "acc1", [VSRp2, VSRp3]>, DwarfRegNum<[-1, -1]>;
41 def ACC2 : ACC<2, "acc2", [VSRp4, VSRp5]>, DwarfRegNum<[-1, -1]>;
42 def ACC3 : ACC<3, "acc3", [VSRp6, VSRp7]>, DwarfRegNum<[-1, -1]>;
43 def ACC4 : ACC<4, "acc4", [VSRp8, VSRp9]>, DwarfRegNum<[-1, -1]>;
44 def ACC5 : ACC<5, "acc5", [VSRp10, VSRp11]>, DwarfRegNum<[-1, -1]>;
45 def ACC6 : ACC<6, "acc6", [VSRp12, VSRp13]>, DwarfRegNum<[-1, -1]>;
46 def ACC7 : ACC<7, "acc7", [VSRp14, VSRp15]>, DwarfRegNum<[-1, -1]>;
64 def UACC0 : UACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>;
[all …]
H A DPPCRegisterInfoDMR.td77 def DMRROW#Index : DMRROW<Index, "dmrrow"#Index>, DwarfRegNum<[-1, -1]>;
89 !cast<DMRROW>("DMRROW"#!add(!mul(Index, 2), 1))]>, DwarfRegNum<[-1, -1]>;
101 !cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 1))]>, DwarfRegNum<[-1, -1]>;
111 !cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 3))]>, DwarfRegNum<[-1, -1]>;
121 … "dmr"#Index, [!cast<WACC>("WACC"#Index), !cast<WACC_HI>("WACC_HI"#Index)]>, DwarfRegNum<[-1, -1]>;
130 def DMRp0 : DMRp<0, "dmrp0", [DMR0, DMR1]>, DwarfRegNum<[-1, -1]>;
131 def DMRp1 : DMRp<1, "dmrp1", [DMR2, DMR3]>, DwarfRegNum<[-1, -1]>;
132 def DMRp2 : DMRp<2, "dmrp2", [DMR4, DMR5]>, DwarfRegNum<[-1, -1]>;
133 def DMRp3 : DMRp<3, "dmrp3", [DMR6, DMR7]>, DwarfRegNum<[-1, -1]>;
H A DPPCRegisterInfo.td130 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
142 DwarfRegNum<[Index, -2]>;
148 DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;
156 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
185 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
192 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
213 DwarfRegNum<[-1, -1]>;
280 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
281 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
282 def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td66 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
67 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
68 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
69 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
70 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
71 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
72 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
73 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
74 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
75 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td79 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
80 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
81 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
82 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
83 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
84 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
85 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
86 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
89 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
90 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td105 def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>;
112 DwarfRegNum<[I]>;
117 def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>;
118 def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>;
119 def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>;
120 def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>;
121 def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>;
122 def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>;
123 def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>;
128 ["s"#I]>, DwarfRegNum<[I]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp267 uint64_t DwarfRegNum; in prettyPrintRegisterOp() local
272 DwarfRegNum = Operands[OpNum++]; in prettyPrintRegisterOp()
274 DwarfRegNum = Opcode - DW_OP_breg0; in prettyPrintRegisterOp()
276 DwarfRegNum = Opcode - DW_OP_reg0; in prettyPrintRegisterOp()
278 auto RegName = DumpOpts.GetNameForDWARFReg(DwarfRegNum, DumpOpts.IsEH); in prettyPrintRegisterOp()
453 uint64_t DwarfRegNum = Op.getRawOperand(0); in printCompactDWARFExpr() local
454 auto RegName = GetNameForDWARFReg(DwarfRegNum, false); in printCompactDWARFExpr()
462 int DwarfRegNum = Op.getRawOperand(0); in printCompactDWARFExpr() local
464 auto RegName = GetNameForDWARFReg(DwarfRegNum, false); in printCompactDWARFExpr()
505 uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0; in printCompactDWARFExpr() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DStackMaps.cpp284 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand()
285 unsigned LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false);
291 DwarfRegNum, Offset); in print()
365 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "
375 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI); in parseRegisterLiveOutMask()
377 return LiveOutReg(Reg, DwarfRegNum, Size); in parseRegisterLiveOutMask()
399 return LHS.DwarfRegNum < RHS.DwarfRegNum; in parseRegisterLiveOutMask()
404 if (I->DwarfRegNum != II->DwarfRegNum) { in parseRegisterLiveOutMask()
269 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); parseOperand() local
360 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI); createLiveOutReg() local
[all...]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DStackMaps.h282 uint16_t DwarfRegNum = 0; member
286 LiveOutReg(uint16_t Reg, uint16_t DwarfRegNum, uint16_t Size) in LiveOutReg()
287 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {} in LiveOutReg()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp181 int DwarfRegNum = getDwarfRegNum(*LRegNum, false); in getDwarfRegNumFromDwarfEHRegNum() local
182 if (DwarfRegNum == -1) in getDwarfRegNumFromDwarfEHRegNum()
185 return DwarfRegNum; in getDwarfRegNumFromDwarfEHRegNum()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td33 def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>;
35 def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td87 DwarfRegNum<[I]>;
228 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
233 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
262 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
337 def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>;
347 def C#I : CREG64<I, "c"#I>, DwarfRegNum<[!add(I, 32)]>;
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp399 for (auto &DwarfRegNum : DwarfRegNums) in EmitRegMappingTables() local
400 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) in EmitRegMappingTables()
401 DwarfRegNum.second.push_back(-1); in EmitRegMappingTables()
420 for (auto &DwarfRegNum : DwarfRegNums) { in EmitRegMappingTables() local
421 int DwarfRegNo = DwarfRegNum.second[I]; in EmitRegMappingTables()
424 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; in EmitRegMappingTables()
481 for (auto &DwarfRegNum : DwarfRegNums) { in EmitRegMappingTables() local
482 int RegNo = DwarfRegNum.second[i]; in EmitRegMappingTables()
486 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()

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