| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 326 mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs, in mergeVectorRegsToResultRegs() argument
329 LLT LLTy = MRI.getType(DstRegs[0]); in mergeVectorRegsToResultRegs()
336 assert(DstRegs.size() == 1); in mergeVectorRegsToResultRegs()
337 return B.buildConcatVectors(DstRegs[0], SrcRegs); in mergeVectorRegsToResultRegs()
344 assert(DstRegs.size() == 1); in mergeVectorRegsToResultRegs()
346 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs)); in mergeVectorRegsToResultRegs()
357 llvm::copy(DstRegs, PadDstRegs.begin()); in mergeVectorRegsToResultRegs()
360 for (int I = DstRegs.size(); I != NumDst; ++I) in mergeVectorRegsToResultRegs()
364 return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg); in mergeVectorRegsToResultRegs()
557 static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs, in buildCopyToRegs() argument
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| H A D | LegalizerHelper.cpp | 1516 SmallVector<Register, 2> DstRegs; in narrowScalar() local
1518 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()
1521 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
1523 MIRBuilder.buildMergeLikeInstr(DstReg, DstRegs); in narrowScalar()
1752 SmallVector<Register, 2> DstRegs(NumParts); in narrowScalar() local
1764 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar()
1766 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); in narrowScalar()
1771 MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), DstRegs); in narrowScalar()
1944 SmallVector<Register, 2> DstRegs; in narrowScalar() local
1967 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
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| H A D | IRTranslator.cpp | 1494 auto &DstRegs = allocateVRegs(U); in translateExtractValue() local
1496 for (unsigned i = 0; i < DstRegs.size(); ++i) in translateExtractValue()
1497 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
1506 auto &DstRegs = allocateVRegs(U); in translateInsertValue() local
1512 for (unsigned i = 0; i < DstRegs.size(); ++i) { in translateInsertValue()
1514 DstRegs[i] = *InsertedIt++; in translateInsertValue()
1516 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
3478 const ArrayRef<Register> DstRegs = getOrCreateVRegs(U); in translateFreeze() local
3481 assert(DstRegs.size() == SrcRegs.size() && in translateFreeze()
3484 for (unsigned I = 0; I < DstRegs.size(); ++I) { in translateFreeze()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 495 SmallVector<Register, 8> DstRegs(NewNumDefs); in tryFoldUnmergeCast()
498 DstRegs[Idx] = MI.getOperand(Idx).getReg(); in tryFoldUnmergeCast()
500 DstRegs[Idx] = MRI.createGenericVirtualRegister(DestTy); in tryFoldUnmergeCast()
505 Builder.buildUnmerge(DstRegs, CastSrcReg); in tryFoldUnmergeCast()
506 UpdatedDefs.append(DstRegs.begin(), DstRegs.begin() + NewNumDefs); in tryFoldUnmergeCast()
1166 SmallVector<Register, 8> DstRegs; in tryCombineUnmergeValues() local
1169 DstRegs.push_back(MI.getReg(DefIdx)); in tryCombineUnmergeValues()
1195 Builder.buildUnmerge(DstRegs, TmpReg); in tryCombineUnmergeValues()
1197 Builder.buildUnmerge(DstRegs, MergeI->getOperand(Idx + 1).getReg()); in tryCombineUnmergeValues()
1199 UpdatedDefs.append(DstRegs.begin(), DstRegs.end()); in tryCombineUnmergeValues()
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| H A D | LegalizerHelper.h | 256 void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ControlFlowFinalizer.cpp | 265 std::set<unsigned> &DstRegs) const { in isCompatibleWithClause()
292 if ((DstRegs.find(SrcMI) == DstRegs.end())) { in isCompatibleWithClause()
293 DstRegs.insert(DstMI); in isCompatibleWithClause()
306 std::set<unsigned> DstRegs; in MakeFetchClause() local
315 if (!isCompatibleWithClause(*I, DstRegs)) in MakeFetchClause()
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| H A D | AMDGPURegisterBankInfo.cpp | 1990 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0)); in foldExtractEltToCmpSelect() local
1991 unsigned NumLanes = DstRegs.size(); in foldExtractEltToCmpSelect()
1995 EltTy = MRI.getType(DstRegs[0]); in foldExtractEltToCmpSelect()
2020 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L]; in foldExtractEltToCmpSelect()
2668 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0)); in applyMappingImpl() local
2676 B.buildFreeze(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2680 B.buildSExtInReg(DstRegs[0], Freeze, Amt); in applyMappingImpl()
2683 B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31)); in applyMappingImpl()
2687 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2688 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32); in applyMappingImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 855 SmallSet<unsigned, 4> DstRegs; in copyPhysReg() local
862 assert(!DstRegs.count(Src) && "destructive vector copy"); in copyPhysReg()
863 DstRegs.insert(Dst); in copyPhysReg()
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