1481   auto &DstRegs = allocateVRegs(U);  in translateExtractValue()  local
1483   for (unsigned i = 0; i < DstRegs.size(); ++i)  in translateExtractValue()
1484     DstRegs[i] = SrcRegs[Idx++];  in translateExtractValue()
1493   auto &DstRegs = allocateVRegs(U);  in translateInsertValue()  local
1499   for (unsigned i = 0; i < DstRegs.size(); ++i) {  in translateInsertValue()
1501       DstRegs[i] = *InsertedIt++;  in translateInsertValue()
1503       DstRegs[i] = SrcRegs[i];  in translateInsertValue()
3325   const ArrayRef<Register> DstRegs = getOrCreateVRegs(U);  in translateFreeze()  local
3328   assert(DstRegs.size() == SrcRegs.size() &&  in translateFreeze()
3331   for (unsigned I = 0; I < DstRegs.size(); ++I) {  in translateFreeze()
3332     MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]);  in translateFreeze()