| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGNonTrivialStruct.cpp | 34 enum { DstIdx = 0, SrcIdx = 1 }; enumerator
374 Address DstAddr = StartAddrs[DstIdx]; in visitArray()
402 CGF.Builder.CreateICmpEQ(PHIs[DstIdx], DstArrayEnd, "done"); in visitArray()
530 Address DstAddr = this->getAddrWithOffset(Addrs[DstIdx], this->Start); in flushTrivialFields()
565 Address DstAddr = this->getAddrWithOffset(Addrs[DstIdx], Offset); in visitVolatileTrivial()
575 Address DstAddr = Addrs[DstIdx].withElementType(Ty); in visitVolatileTrivial()
586 Addrs[DstIdx] = this->getAddrWithOffset(Addrs[DstIdx], CurStackOffset, FD); in visitPtrAuth()
588 this->CGF->EmitPointerAuthCopy(PtrAuth, FT, Addrs[DstIdx], Addrs[SrcIdx]); in visitPtrAuth()
613 *CGF, getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT); in visitARCStrong()
619 *CGF, getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT); in visitARCWeak()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.h | 40 unsigned DstIdx = 0; variable
104 unsigned getDstIdx() const { return DstIdx; } in getDstIdx()
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| H A D | TwoAddressInstructionPass.cpp | 153 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
171 unsigned SrcIdx, unsigned DstIdx,
742 unsigned DstIdx, in commuteInstruction() argument
763 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
1316 unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) { in tryInstructionTransform() argument
1321 Register regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1330 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1522 unsigned DstIdx = 0; in collectTiedOperands() local
1523 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1527 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands()
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| H A D | RegisterCoalescer.cpp | 265 unsigned DstIdx);
460 SrcIdx = DstIdx = 0; in setRegisters()
510 DstIdx); in setRegisters()
519 DstIdx = SrcSub; in setRegisters()
532 if (DstIdx && !SrcIdx) { in setRegisters()
534 std::swap(SrcIdx, DstIdx); in setRegisters()
552 std::swap(SrcIdx, DstIdx); in flip()
577 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
592 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1307 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx(); in reMaterializeTrivialDef() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 87 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction() local
88 assert(DstIdx != -1); in runOnMachineFunction()
89 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction()
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| H A D | R600Packetizer.cpp | 84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector() local
85 if (DstIdx == -1) { in getPreviousVector()
88 Register Dst = BI->getOperand(DstIdx).getReg(); in getPreviousVector()
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| H A D | SIPeepholeSDWA.cpp | 487 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertToSDWA() local
489 auto TiedIdx = MI.findTiedOperandIdx(DstIdx); in convertToSDWA()
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| H A D | R600ISelLowering.cpp | 228 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter() local
229 assert(DstIdx != -1); in EmitInstrWithCustomInserter()
233 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) || in EmitInstrWithCustomInserter()
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| H A D | SIInstrInfo.cpp | 4960 int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in verifyInstruction() local
4962 for (int OpIdx : {DstIdx, Src0Idx, Src1Idx, Src2Idx}) { in verifyInstruction()
5009 if (!ST.hasSDWASdst() && DstIdx != -1) { in verifyInstruction()
5011 const MachineOperand &Dst = MI.getOperand(DstIdx); in verifyInstruction()
5036 const MachineOperand &Dst = MI.getOperand(DstIdx); in verifyInstruction()
5043 MI.getOperand(MI.findTiedOperandIdx(DstIdx)); in verifyInstruction()
5076 const uint32_t DstIdx = in verifyInstruction() local
5078 const MachineOperand &Dst = MI.getOperand(DstIdx); in verifyInstruction()
5080 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
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| H A D | SIISelLowering.cpp | 16169 int DstIdx = in AddMemOpInit() local
16211 TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddMemOpInit()
16215 InitIdx = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddMemOpInit()
16223 Register PrevDst = MRI.cloneVirtualRegister(MI.getOperand(DstIdx).getReg()); in AddMemOpInit()
16234 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddMemOpInit()
16254 MI.tieOperands(DstIdx, MI.getNumOperands() - 1); in AddMemOpInit()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | GISelValueTracking.cpp | 547 unsigned DstIdx = 0; in computeKnownBitsImpl() local
548 for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R; in computeKnownBitsImpl()
549 ++DstIdx) in computeKnownBitsImpl()
556 DemandedElts.zext(SrcTy.getNumElements()).shl(DstIdx * DstLanes); in computeKnownBitsImpl()
565 Known = SrcOpKnown.extractBits(BitWidth, BitWidth * DstIdx); in computeKnownBitsImpl()
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| H A D | LegalizerHelper.cpp | 6510 unsigned DstIdx = 0; // Low bits of the result. in multiplyRegisters() local
6512 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
6513 DstRegs[DstIdx] = FactorSum; in multiplyRegisters()
6518 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { in multiplyRegisters()
6520 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; in multiplyRegisters()
6521 i <= std::min(DstIdx, SrcParts - 1); ++i) { in multiplyRegisters()
6523 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
6527 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; in multiplyRegisters()
6528 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { in multiplyRegisters()
6530 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); in multiplyRegisters()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | WebAssembly.cpp | 614 Value *DstIdx = EmitScalarExpr(E->getArg(2)); in EmitWebAssemblyBuiltinExpr() local
620 return Builder.CreateCall(Callee, {TableX, TableY, SrcIdx, DstIdx, NElems}); in EmitWebAssemblyBuiltinExpr()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 1019 unsigned DstIdx = (Elt0UnmergeIdx * EltSize) / DstTy.getSizeInBits(); in tryCombineMergeLike() local
1020 replaceRegOrBuildCopy(Dst, NewUnmerge.getReg(DstIdx), MRI, MIB, in tryCombineMergeLike()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 402 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeAVLdSt() local
403 if (IsAGPROperand(Inst, DstIdx, MRI)) in decodeAVLdSt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 2416 unsigned DstIdx = (Imm >> 4) & 3; in commuteInstructionImpl() local
2421 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 && in commuteInstructionImpl()
2423 unsigned AltIdx = llvm::countr_zero((ZMask | (1 << DstIdx)) ^ 15); in commuteInstructionImpl()
7315 unsigned DstIdx = (Imm >> 4) & 3; in foldMemoryOperandCustom() local
7324 unsigned NewImm = (DstIdx << 4) | ZMask; in foldMemoryOperandCustom()
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| H A D | X86ISelLowering.cpp | 6326 unsigned DstIdx = 0; in getFauxShuffleMask() local
6332 DstIdx = N.getConstantOperandVal(2); in getFauxShuffleMask()
6338 Mask.push_back(i == DstIdx ? SM_SentinelZero : (int)i); in getFauxShuffleMask()
6377 unsigned DstByte = DstIdx * NumBytesPerElt; in getFauxShuffleMask()
42847 unsigned DstIdx = (InsertPSMask >> 4) & 0x3; in combineTargetShuffle() local
42851 if (((ZeroMask | (1u << DstIdx)) == 0xF) && !Op0.isUndef()) in combineTargetShuffle()
42856 if ((ZeroMask & (1u << DstIdx)) && !Op1.isUndef()) in combineTargetShuffle()
42868 InsertPSMask |= (1u << DstIdx); in combineTargetShuffle()
42891 if ((InsertPSMask & (1u << i)) || (i == (int)DstIdx)) { in combineTargetShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 8967 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in cvtVOP3DstOpSelOnly() local
8968 if (DstIdx == -1) in cvtVOP3DstOpSelOnly()
8971 const MCOperand &DstOp = Inst.getOperand(DstIdx); in cvtVOP3DstOpSelOnly()
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