| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTfrCleanup.cpp | 127 unsigned DefR = MI->getOperand(0).getReg(); in updateImmMap() local
129 if (!isIntReg(DefR, Is32)) in updateImmMap()
133 IMap.erase(TRI->getSubReg(DefR, isub_lo)); in updateImmMap()
134 IMap.erase(TRI->getSubReg(DefR, isub_hi)); in updateImmMap()
136 IMap.erase(DefR); in updateImmMap()
144 setReg(TRI->getSubReg(DefR, isub_lo), VL, IMap); in updateImmMap()
145 setReg(TRI->getSubReg(DefR, isub_hi), VH, IMap); in updateImmMap()
147 setReg(DefR, Val, IMap); in updateImmMap()
225 unsigned DefR, SrcR; in eraseIfRedundant() local
230 DefR = MI->getOperand(0).getReg(); in eraseIfRedundant()
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| H A D | HexagonConstPropagation.cpp | 614 RegSubRegPair DefR(getRegSubRegPair(MD)); in visitPHI() local
615 assert(DefR.Reg.isVirtual()); in visitPHI()
620 if (DefR.SubReg) { in visitPHI()
622 const LatticeCell &T = Cells.get(DefR.Reg); in visitPHI()
624 Cells.update(DefR.Reg, Bottom); in visitPHI()
626 visitUsesOf(DefR.Reg); in visitPHI()
630 LatticeCell DefC = Cells.get(DefR.Reg); in visitPHI()
657 Cells.update(DefR.Reg, DefC); in visitPHI()
662 visitUsesOf(DefR.Reg); in visitPHI()
684 RegSubRegPair DefR(getRegSubRegPair(MO)); in visitNonBranch() local
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| H A D | HexagonGenMux.cpp | 100 unsigned DefR, PredR; member
107 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
328 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
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| H A D | HexagonCopyHoisting.cpp | 215 Register DefR = CandMI->getOperand(0).getReg(); in isSafetoMove() local
224 if (Mo.isReg() && Mo.getReg() == DefR) in isSafetoMove()
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| H A D | HexagonConstExtenders.cpp | 1514 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer() local
1528 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1535 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1540 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1545 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1554 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) in insertInitializer()
1567 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1571 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1583 return { DefR, 0 }; in insertInitializer()
1909 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
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| H A D | HexagonEarlyIfConv.cpp | 434 Register DefR = MI.getOperand(0).getReg(); in isValid() local
435 if (isPredicate(DefR)) in isValid()
984 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
991 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
996 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
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| H A D | HexagonBitSimplify.cpp | 1228 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1229 if (!DefR.isVirtual()) in computeUsedBits()
1231 Pending.push_back(DefR); in computeUsedBits()
2924 unsigned DefR; member
2931 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2932 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2950 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2985 unsigned DefR) const { in isBitShuffle()
3137 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3165 Register DefR = Defs.find_first(); in processLoop() local
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| H A D | HexagonOptAddrMode.cpp | 104 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
1090 Register DefR = MI->getOperand(0).getReg(); in processBlock() local
1095 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
1119 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
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| H A D | HexagonBitTracker.cpp | 958 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
959 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
960 BT::RegisterRef PD(DefR, 0); in evaluate()
963 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanPatternMatch.h | 215 auto *DefR = V->getDefiningRecipe(); in match() local
216 return DefR && match(DefR); in match()
253 auto *DefR = dyn_cast<RecipeTy>(R); in matchRecipeAndOpcode() local
260 return DefR; in matchRecipeAndOpcode()
262 return DefR && DefR->getOpcode() == Opcode; in matchRecipeAndOpcode()
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| H A D | VPlanAnalysis.cpp | 449 auto *DefR = U->getDefiningRecipe(); in calculateRegisterUsageForPlan() local
455 if (!DefR && (!U->getLiveInIRValue() || in calculateRegisterUsageForPlan()
460 if (!DefR) { in calculateRegisterUsageForPlan()
466 EndPoint[DefR] = Idx2Recipe.size(); in calculateRegisterUsageForPlan()
467 Ends.insert(DefR); in calculateRegisterUsageForPlan()
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| H A D | VPlan.cpp | 1446 const VPRecipeBase *DefR = VPV->getDefiningRecipe(); in isDefinedInsideLoopRegions() local
1447 return DefR && (!DefR->getParent()->getPlan()->getVectorLoopRegion() || in isDefinedInsideLoopRegions()
1448 DefR->getParent()->getEnclosingLoopRegion()); in isDefinedInsideLoopRegions()
1602 const VPRecipeBase *DefR = V->getDefiningRecipe(); in getOrCreateName() local
1603 (void)DefR; in getOrCreateName()
1604 assert((!DefR || !DefR->getParent() || !DefR->getParent()->getPlan()) && in getOrCreateName()
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| H A D | VPlanTransforms.cpp | 3095 auto *DefR = OpV->getDefiningRecipe(); in canNarrowLoad() local
3096 if (!DefR) in canNarrowLoad()
3098 if (auto *W = dyn_cast<VPWidenLoadRecipe>(DefR)) in canNarrowLoad()
3101 if (auto *IR = dyn_cast<VPInterleaveRecipe>(DefR)) in canNarrowLoad()
3217 VPRecipeBase *DefR = Op.value()->getDefiningRecipe(); in narrowInterleaveGroups() local
3218 if (!DefR) in narrowInterleaveGroups()
3220 auto *IR = dyn_cast<VPInterleaveRecipe>(DefR); in narrowInterleaveGroups()
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