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Searched refs:DefR (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h117 auto *DefR = dyn_cast<RecipeTy>(R);
118 return DefR && DefR->getOpcode() == Opcode;
138 auto *DefR = V->getDefiningRecipe();
139 return DefR && match(DefR);
169 auto *DefR = V->getDefiningRecipe();
170 return DefR && match(DefR);
309 auto *DefR = V->getDefiningRecipe();
310 return DefR && match(DefR);
327 auto *DefR = V->getDefiningRecipe();
328 return DefR && match(DefR);
H A DVPlan.cpp1584 const VPRecipeBase *DefR = V->getDefiningRecipe(); in getOrCreateName() local
1585 (void)DefR; in getOrCreateName()
1586 assert((!DefR || !DefR->getParent() || !DefR->getParent()->getPlan()) && in getOrCreateName()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTfrCleanup.cpp143 unsigned DefR = MI->getOperand(0).getReg(); in updateImmMap() local
145 if (!isIntReg(DefR, Is32)) in updateImmMap()
149 IMap.erase(TRI->getSubReg(DefR, isub_lo)); in updateImmMap()
150 IMap.erase(TRI->getSubReg(DefR, isub_hi)); in updateImmMap()
152 IMap.erase(DefR); in updateImmMap()
160 setReg(TRI->getSubReg(DefR, isub_lo), VL, IMap); in updateImmMap()
161 setReg(TRI->getSubReg(DefR, isub_hi), VH, IMap); in updateImmMap()
163 setReg(DefR, Val, IMap); in updateImmMap()
244 unsigned DefR, SrcR; in eraseIfRedundant() local
249 DefR = MI->getOperand(0).getReg(); in eraseIfRedundant()
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H A DHexagonConstPropagation.cpp633 RegisterSubReg DefR(MD); in visitPHI() local
634 assert(DefR.Reg.isVirtual()); in visitPHI()
639 if (DefR.SubReg) { in visitPHI()
641 const LatticeCell &T = Cells.get(DefR.Reg); in visitPHI()
643 Cells.update(DefR.Reg, Bottom); in visitPHI()
645 visitUsesOf(DefR.Reg); in visitPHI()
649 LatticeCell DefC = Cells.get(DefR.Reg); in visitPHI()
676 Cells.update(DefR.Reg, DefC); in visitPHI()
681 visitUsesOf(DefR.Reg); in visitPHI()
703 RegisterSubReg DefR(M in visitNonBranch() local
1935 RegisterSubReg DefR(MD); evaluate() local
2584 RegisterSubReg DefR(MI.getOperand(0)); evaluateHexCompare() local
2668 RegisterSubReg DefR(MI.getOperand(0)); evaluateHexLogical() local
2692 RegisterSubReg DefR(MI.getOperand(0)); evaluateHexCondMove() local
2750 RegisterSubReg DefR(MI.getOperand(0)); evaluateHexExt() local
2764 RegisterSubReg DefR(MI.getOperand(0)); evaluateHexVector1() local
2974 RegisterSubReg DefR(MI.getOperand(0)); rewriteHexConstUses() local
3058 RegisterSubReg DefR(MI.getOperand(0)); rewriteHexConstUses() local
3090 RegisterSubReg DefR(MI.getOperand(0)); rewriteHexConstUses() local
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H A DHexagonGenMux.cpp108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
337 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
H A DHexagonCopyHoisting.cpp221 Register DefR = CandMI->getOperand(0).getReg(); in isSafetoMove() local
230 if (Mo.isReg() && Mo.getReg() == DefR) in isSafetoMove()
H A DHexagonConstExtenders.cpp1533 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer() local
1547 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1564 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1573 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) in insertInitializer()
1586 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1590 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1602 return { DefR, 0 }; in insertInitializer()
1928 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
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H A DHexagonEarlyIfConv.cpp441 Register DefR = MI.getOperand(0).getReg(); in isValid() local
442 if (isPredicate(DefR)) in isValid()
991 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
998 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
1003 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
H A DHexagonBitSimplify.cpp1250 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1251 if (!DefR.isVirtual()) in computeUsedBits()
1253 Pending.push_back(DefR); in computeUsedBits()
2955 unsigned DefR; member
2962 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2963 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2981 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
3016 unsigned DefR) const { in isBitShuffle()
3168 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3196 Register DefR = Defs.find_first(); in processLoop() local
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H A DHexagonOptAddrMode.cpp99 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
807 Register DefR = MI->getOperand(0).getReg(); in processBlock() local
812 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
836 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
H A DHexagonBitTracker.cpp966 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
967 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
968 BT::RegisterRef PD(DefR, 0); in evaluate()
971 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()