Lines Matching refs:DefR

633   RegisterSubReg DefR(MD);
634   assert(DefR.Reg.isVirtual());
639   if (DefR.SubReg) {
641     const LatticeCell &T = Cells.get(DefR.Reg);
643     Cells.update(DefR.Reg, Bottom);
645       visitUsesOf(DefR.Reg);
649   LatticeCell DefC = Cells.get(DefR.Reg);
676     Cells.update(DefR.Reg, DefC);
681     visitUsesOf(DefR.Reg);
703     RegisterSubReg DefR(MO);
705     if (!DefR.Reg.isVirtual())
710       const LatticeCell &T = Cells.get(DefR.Reg);
712       Cells.update(DefR.Reg, Bottom);
716       if (!Outputs.has(DefR.Reg))
718       LatticeCell RC = Cells.get(DefR.Reg);
719       Changed = RC.meet(Outputs.get(DefR.Reg));
720       Cells.update(DefR.Reg, RC);
723       visitUsesOf(DefR.Reg);
1935   RegisterSubReg DefR(MD);
1936   assert(!DefR.SubReg);
1937   if (!DefR.Reg.isVirtual())
1946     Outputs.update(DefR.Reg, RC);
1952     const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
1968     Outputs.update(DefR.Reg, RC);
1991       unsigned W = getRegBitWidth(DefR.Reg);
1997       LatticeCell RC = Outputs.get(DefR.Reg);
1999       Outputs.update(DefR.Reg, RC);
2006       LatticeCell RC = Outputs.get(DefR.Reg);
2011       Outputs.update(DefR.Reg, RC);
2040       LatticeCell RC = Outputs.get(DefR.Reg);
2042       Outputs.update(DefR.Reg, RC);
2052       LatticeCell RC = Outputs.get(DefR.Reg);
2056       Outputs.update(DefR.Reg, RC);
2101       LatticeCell RC = Outputs.get(DefR.Reg);
2108       Outputs.update(DefR.Reg, RC);
2133       LatticeCell RC = Outputs.get(DefR.Reg);
2140       Outputs.update(DefR.Reg, RC);
2155       LatticeCell RC = Outputs.get(DefR.Reg);
2171       Outputs.update(DefR.Reg, RC);
2584       RegisterSubReg DefR(MI.getOperand(0));
2585       LatticeCell L = Outputs.get(DefR.Reg);
2589       Outputs.update(DefR.Reg, L);
2668     RegisterSubReg DefR(MI.getOperand(0));
2669     Outputs.update(DefR.Reg, RC);
2692   RegisterSubReg DefR(MI.getOperand(0));
2693   LatticeCell RC = Outputs.get(DefR.Reg);
2697     unsigned W = getRegBitWidth(DefR.Reg);
2701     Outputs.update(DefR.Reg, RC);
2711     Outputs.update(DefR.Reg, RC);
2750   RegisterSubReg DefR(MI.getOperand(0));
2751   unsigned BW = getRegBitWidth(DefR.Reg);
2752   LatticeCell RC = Outputs.get(DefR.Reg);
2757   Outputs.update(DefR.Reg, RC);
2763   // DefR = op R1
2764   RegisterSubReg DefR(MI.getOperand(0));
2767   LatticeCell RC = Outputs.get(DefR.Reg);
2786   Outputs.update(DefR.Reg, RC);
2969     // Convert DefR += mpyi(R2, R3)
2970     //   to   DefR += mpyi(R, #imm),
2971     //   or   DefR -= mpyi(R, #imm).
2973       RegisterSubReg DefR(MI.getOperand(0));
2974       assert(!DefR.SubReg);
2988         // DefR == R1 (tied operands).
2994           const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
2999         replaceAllRegUsesWith(DefR.Reg, NewR);
3023       const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3030       replaceAllRegUsesWith(DefR.Reg, NewR);
3057       RegisterSubReg DefR(MI.getOperand(0));
3060         const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3065       replaceAllRegUsesWith(DefR.Reg, NewR);
3089       RegisterSubReg DefR(MI.getOperand(0));
3092         const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3097       replaceAllRegUsesWith(DefR.Reg, NewR);