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Searched refs:DefIdx (Results 1 – 25 of 45) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h183 /// instruction of itinerary class DefClass, operand index DefIdx can be
186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
208 std::optional<unsigned> getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
214 std::optional<unsigned> DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
224 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
184 hasPipelineForwarding(unsigned DefClass,unsigned DefIdx,unsigned UseClass,unsigned UseIdx) hasPipelineForwarding() argument
205 getOperandLatency(unsigned DefClass,unsigned DefIdx,unsigned UseClass,unsigned UseIdx) getOperandLatency() argument
H A DMCSubtargetInfo.h177 unsigned DefIdx) const { in getWriteLatencyEntry() argument
178 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
181 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp146 unsigned DefIdx = 0; in findDefIdx()
150 ++DefIdx;
152 return DefIdx;
202 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
203 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
206 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
222 // If DefIdx does not exist in the model (e.g. implicit defs), then return in computeOperandLatency()
228 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
142 unsigned DefIdx = 0; findDefIdx() local
H A DLiveIntervalCalc.cpp35 SlotIndex DefIdx = in createDeadDef()
39 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
180 unsigned DefIdx; in extendToUses()
183 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
186 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
36 SlotIndex DefIdx = createDeadDef() local
181 unsigned DefIdx; extendToUses() local
H A DPeepholeOptimizer.cpp416 unsigned DefIdx = 0; member in __anon776574090111::ValueTracker
470 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1892 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1913 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1920 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1957 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1980 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
2001 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
2014 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
2030 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
[all …]
H A DTargetInstrInfo.cpp1443 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1453 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1455 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1517 unsigned DefIdx) const { in hasLowDefLatency()
1524 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1645 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { in getOperandLatency() argument
1648 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1652 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1658 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1662 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
[all …]
H A DLiveRangeEdit.cpp167 SlotIndex DefIdx; in canRematerializeAt() local
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineVerifier.cpp284 SlotIndex DefIdx, const LiveRange &LR,
2494 unsigned DefIdx; in visitMachineOperand() local
2497 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
2498 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
2739 unsigned MONum, SlotIndex DefIdx, in checkLivenessAtDef() argument
2744 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
2753 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) || in checkLivenessAtDef()
2754 !SlotIndex::isSameInstr(VNI->def, DefIdx) || in checkLivenessAtDef()
2755 (VNI->def != DefIdx && in checkLivenessAtDef()
2756 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) { in checkLivenessAtDef()
[all …]
H A DMachineInstr.cpp280 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
281 if (DefIdx != -1) in addOperand()
282 tieOperands(DefIdx, OpNo); in addOperand()
960 unsigned DefIdx; in getRegClassConstraint() local
961 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
962 OpIdx = DefIdx; in getRegClassConstraint()
1162 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1163 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1170 if (DefIdx < TiedMax) in tieOperands()
1171 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h591 unsigned DefIdx = 0; in getDefIndex() local
595 ++DefIdx; in getDefIndex()
598 return DefIdx; in getDefIndex()
896 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeDefs() local
897 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
899 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
912 MI.getOperand(DefIdx).setReg(DefReg); in tryCombineUnmergeDefs()
914 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
1154 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineUnmergeValues() local
1155 ++j, ++DefIdx) in tryCombineUnmergeValues()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp45 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
46 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
49 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp623 int DefIdx = SwapMap[DefMI]; in formWebs() local
624 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
628 SwapVector[DefIdx].VSEId, in formWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
729 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
736 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
804 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h339 unsigned DefIdx,
343 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
346 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
352 unsigned DefIdx) const override { in hasLowDefLatency() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h66 const MachineInstr &MI, unsigned DefIdx,
79 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
95 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
326 unsigned DefIdx,
330 SDNode *DefNode, unsigned DefIdx,
433 unsigned DefClass, unsigned DefIdx,
437 unsigned DefClass, unsigned DefIdx,
449 unsigned DefIdx, unsigned DefAlign,
456 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
471 const MachineInstr &DefMI, unsigned DefIdx,
[all …]
H A DARMBaseInstrInfo.cpp3879 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3880 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3883 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3919 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3920 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3923 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
4019 unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, in getOperandLatency() argument
4024 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
4025 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
4034 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp399 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP()
402 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers)) in handleADRP()
567 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction()
569 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
570 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()
403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); handleADRP() local
571 int DefIdx = mapRegToGPRIndex(Def.getReg()); runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency()
219 DefIdx != DefEnd; ++DefIdx) { in getLatency()
222 DefIdx); in getLatency()
217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; getLatency() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
160 return DefIdx-1; in GetIdx()
H A DScheduleDAGSDNodes.cpp479 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
516 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep, nullptr); in AddSchedEdges()
579 DefIdx = 0; in InitNodeNumDefs()
593 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
594 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
596 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
597 ++DefIdx; in Advance()
659 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
664 TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h548 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
566 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
586 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1378 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1392 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1406 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1771 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1783 const MachineInstr &DefMI, unsigned DefIdx,
1812 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1822 unsigned DefIdx) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp214 unsigned DefIdx = 0; in tryInlineAsm() local
218 if (Changed && Flag.isUseOperandTiedToDef(DefIdx)) in tryInlineAsm()
219 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
303 Flag.setMatchingOp(DefIdx); in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp169 unsigned DefIdx = 0; in selectInlineAsm() local
173 if (Changed && Flag.isUseOperandTiedToDef(DefIdx)) in selectInlineAsm()
174 IsTiedToChangedOp = OpChanged[DefIdx]; in selectInlineAsm()
259 Flag.setMatchingOp(DefIdx); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp560 int DefIdx = -1; in restoreLatency() local
572 DefIdx = OpNum; in restoreLatency()
575 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
582 &InstrItins, *SrcI, DefIdx, *DstI, OpNum); in restoreLatency()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp383 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
386 for (unsigned i = 0; i < DefIdx; ++i) in lowerInlineAsm()
419 UseFlag.setMatchingOp(DefIdx); in lowerInlineAsm()

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