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Searched refs:DefIdx (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h183 /// instruction of itinerary class DefClass, operand index DefIdx can be
186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
208 std::optional<unsigned> getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
214 std::optional<unsigned> DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
224 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
184 hasPipelineForwarding(unsigned DefClass,unsigned DefIdx,unsigned UseClass,unsigned UseIdx) hasPipelineForwarding() argument
205 getOperandLatency(unsigned DefClass,unsigned DefIdx,unsigned UseClass,unsigned UseIdx) getOperandLatency() argument
H A DMCSubtargetInfo.h180 unsigned DefIdx) const { in getWriteLatencyEntry() argument
181 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
184 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp46 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
47 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
50 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
193 for (unsigned DefIdx = 0; DefIdx != DefEnd; ++DefIdx) { in getBypassDelayCycles() local
196 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in getBypassDelayCycles()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp143 unsigned DefIdx = 0; in findDefIdx() local
147 ++DefIdx; in findDefIdx()
149 return DefIdx; in findDefIdx()
199 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
200 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
203 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
225 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
H A DLiveIntervalCalc.cpp34 SlotIndex DefIdx = in createDeadDef() local
38 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
179 unsigned DefIdx; in extendToUses() local
182 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
185 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
H A DPeepholeOptimizer.cpp691 unsigned DefIdx = 0; member in __anon776574090111::ValueTracker
744 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1903 assert(!Def->getOperand(DefIdx).getSubReg() && "no subregister defs in SSA"); in getNextSourceFromCopy()
1923 assert(!Def->getOperand(DefIdx).getSubReg() && "no subregister defs in SSA"); in getNextSourceFromBitcast()
1926 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1946 const MachineOperand &DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1965 assert(!Def->getOperand(DefIdx).getSubReg() && "illegal subregister def"); in getNextSourceFromRegSequence()
1968 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
2026 assert(!Def->getOperand(DefIdx).getSubReg() && "no subreg defs in SSA"); in getNextSourceFromInsertSubreg()
2030 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
[all …]
H A DTargetInstrInfo.cpp1754 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1764 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1766 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1828 unsigned DefIdx) const { in hasLowDefLatency()
1835 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1955 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { in getOperandLatency() argument
1958 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1962 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1968 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1972 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
[all …]
H A DLiveRangeEdit.cpp167 SlotIndex DefIdx; in canRematerializeAt() local
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
172 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineVerifier.cpp335 SlotIndex DefIdx, const LiveRange &LR,
2623 unsigned DefIdx; in visitMachineOperand() local
2625 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
2626 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
2877 unsigned MONum, SlotIndex DefIdx, in checkLivenessAtDef() argument
2888 report_context(DefIdx); in checkLivenessAtDef()
2891 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
2900 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) || in checkLivenessAtDef()
2901 !SlotIndex::isSameInstr(VNI->def, DefIdx) || in checkLivenessAtDef()
2902 (VNI->def != DefIdx && in checkLivenessAtDef()
[all …]
H A DMachineInstr.cpp282 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
283 if (DefIdx != -1) in addOperand()
284 tieOperands(DefIdx, OpNo); in addOperand()
987 unsigned DefIdx; in getRegClassConstraint() local
988 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
989 OpIdx = DefIdx; in getRegClassConstraint()
1189 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1190 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1197 if (DefIdx < TiedMax) { in tieOperands()
1198 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp341 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
342 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h596 unsigned DefIdx = 0; in getDefIndex() local
600 ++DefIdx; in getDefIndex()
603 return DefIdx; in getDefIndex()
901 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeDefs() local
902 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
904 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
917 MI.getOperand(DefIdx).setReg(DefReg); in tryCombineUnmergeDefs()
919 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
1167 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineUnmergeValues() local
1168 ++j, ++DefIdx) in tryCombineUnmergeValues()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp621 int DefIdx = SwapMap[DefMI]; in formWebs() local
622 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
626 SwapVector[DefIdx].VSEId, in formWebs()
725 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
727 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
728 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
734 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
801 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
802 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h449 unsigned DefIdx,
453 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
456 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
462 unsigned DefIdx) const override { in hasLowDefLatency() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h66 const MachineInstr &MI, unsigned DefIdx,
79 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
95 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
323 unsigned DefIdx,
327 SDNode *DefNode, unsigned DefIdx,
424 unsigned DefClass, unsigned DefIdx,
428 unsigned DefClass, unsigned DefIdx,
440 unsigned DefIdx, unsigned DefAlign,
447 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
462 const MachineInstr &DefMI, unsigned DefIdx,
[all …]
H A DARMBaseInstrInfo.cpp3722 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3723 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3726 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3762 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3763 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3766 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3862 unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, in getOperandLatency() argument
3867 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3868 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3877 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp410 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
413 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers)) in handleADRP()
574 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
576 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
577 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp479 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
515 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep, nullptr); in AddSchedEdges()
578 DefIdx = 0; in InitNodeNumDefs()
592 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
593 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
595 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
596 ++DefIdx; in Advance()
658 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
663 TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
160 return DefIdx-1; in GetIdx()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h571 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
589 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
609 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1444 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1458 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1472 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1846 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1858 const MachineInstr &DefMI, unsigned DefIdx,
1887 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1897 unsigned DefIdx) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp212 unsigned DefIdx = 0; in tryInlineAsm() local
216 if (Changed && Flag.isUseOperandTiedToDef(DefIdx)) in tryInlineAsm()
217 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
301 Flag.setMatchingOp(DefIdx); in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp169 unsigned DefIdx = 0; in selectInlineAsm() local
173 if (Changed && Flag.isUseOperandTiedToDef(DefIdx)) in selectInlineAsm()
174 IsTiedToChangedOp = OpChanged[DefIdx]; in selectInlineAsm()
259 Flag.setMatchingOp(DefIdx); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp561 int DefIdx = -1; in restoreLatency() local
573 DefIdx = OpNum; in restoreLatency()
576 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
583 &InstrItins, *SrcI, DefIdx, *DstI, OpNum); in restoreLatency()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp383 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
386 for (unsigned i = 0; i < DefIdx; ++i) in lowerInlineAsm()
419 UseFlag.setMatchingOp(DefIdx); in lowerInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp688 SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot(); in moveAndTeeForMultiUse() local
692 LiveInterval::iterator I = LI.FindSegmentContaining(DefIdx); in moveAndTeeForMultiUse()
693 VNInfo *ValNo = LI.getVNInfoAt(DefIdx); in moveAndTeeForMultiUse()

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