1443                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
1453     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
1455   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1517                                        unsigned DefIdx) const {  in hasLowDefLatency()
1524       ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1645     unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {  in getOperandLatency()  argument
1648   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1652     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1658     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1662   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1679     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1685     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1689   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1704     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1710     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1714   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()