Searched refs:Def1 (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 100 MachineInstr *Def1 = nullptr; in processReg() local
178 if (Def1) in processReg()
180 Def1 = &I; in processReg()
201 if (!Def0 || !Def1 || Def0->getParent() != Def1->getParent()) in processReg()
204 LLVM_DEBUG(dbgs() << "Combining:\n " << *Def0 << " " << *Def1 in processReg()
207 if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1), in processReg()
209 std::swap(Def0, Def1); in processReg()
212 LIS->RemoveMachineInstrFromMaps(*Def1); in processReg()
218 Def1->eraseFromParent(); in processReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 102 MachineInstr *Def1, *Def2; member
107 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
289 MachineInstr &Def1 = *It1, &Def2 = *It2; in genMuxInBlock() local
290 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock()
312 MachineBasicBlock::iterator At = CanDown ? Def2 : Def1; in genMuxInBlock()
313 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); in genMuxInBlock()
323 if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent()) in genMuxInBlock()
333 B.remove(MX.Def1); in genMuxInBlock()
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| H A D | HexagonEarlyIfConv.cpp | 473 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); in computePhiCost() local
475 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3)) in computePhiCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 479 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(), in createCRLogicalOpInfo() local
482 assert(Def1 && "Must be able to find a definition of operand 1."); in createCRLogicalOpInfo()
484 MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg()); in createCRLogicalOpInfo()
498 Ret.TrueDefs = std::make_pair(Def1, Def2); in createCRLogicalOpInfo()
500 Ret.TrueDefs = std::make_pair(Def1, nullptr); in createCRLogicalOpInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1763 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
1766 if (!produceSameValue(*Def0, *Def1, MRI)) in produceSameValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 6415 bool Def1 = !Elems[I1].isUndef(); in buildVector() local
6417 if (Def1 || Def2) { in buildVector()
6418 SDValue Elem1 = Elems[Def1 ? I1 : I2]; in buildVector()
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