/freebsd/contrib/arm-optimized-routines/pl/math/ |
H A D | poly_sve_generic.h | 18 #ifndef DUP 19 # error Cannot use poly_generic without defining DUP 26 VTYPE p01 = svmla_x (pg, DUP (poly[0]), x, poly[1]); in VWRAP() 27 VTYPE p23 = svmla_x (pg, DUP (poly[2]), x, poly[3]); in VWRAP() 41 VTYPE p45 = svmla_x (pg, DUP (poly[4]), x, poly[5]); in VWRAP() 48 VTYPE p45 = svmla_x (pg, DUP (poly[4]), x, poly[5]); in VWRAP() 67 VTYPE p89 = svmla_x (pg, DUP (poly[8]), x, poly[9]); in VWRAP() 73 VTYPE p89 = svmla_x (pg, DUP (poly[8]), x, poly[9]); in VWRAP() 118 VTYPE p16_17 = svmla_x (pg, DUP (poly[16]), x, poly[17]); in VWRAP() 126 VTYPE p16_17 = svmla_x (pg, DUP (poly[16]), x, poly[17]); in VWRAP() [all …]
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H A D | poly_sve_f32.h | 19 #define DUP svdup_f32 macro 21 #undef DUP
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H A D | poly_sve_f64.h | 19 #define DUP svdup_f64 macro 21 #undef DUP
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/freebsd/cddl/contrib/opensolaris/lib/libdtrace/common/ |
H A D | dt_grammar.y | 38 #define DUP(s) strdup(s) macro 396 | DT_KEY_SELF { $$ = dt_node_ident(DUP("self")); } 397 | DT_KEY_THIS { $$ = dt_node_ident(DUP("this")); } 666 type_specifier: DT_KEY_VOID { $$ = dt_decl_spec(CTF_K_INTEGER, DUP("void")); } 667 | DT_KEY_CHAR { $$ = dt_decl_spec(CTF_K_INTEGER, DUP("char")); } 669 | DT_KEY_INT { $$ = dt_decl_spec(CTF_K_INTEGER, DUP("int")); } 671 | DT_KEY_FLOAT { $$ = dt_decl_spec(CTF_K_FLOAT, DUP("float")); } 672 | DT_KEY_DOUBLE { $$ = dt_decl_spec(CTF_K_FLOAT, DUP("double")); } 677 $$ = dt_decl_spec(CTF_K_TYPEDEF, DUP("string")); 875 DT_KEY_PROBE { $$ = DUP("probe"); } [all …]
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/freebsd/crypto/openssl/test/ |
H A D | cmp_ctx_test.c | 336 #define DEFINE_SET_GET_BASE_TEST(PREFIX, SETN, GETN, DUP, FIELD, TYPE, ERR, \ argument 392 if (DUP && val1_read == val1) { \ 421 if (DUP && val2_read == val2) { \ 451 if (DUP && val3_read == val2_read) { \ 513 #define DEFINE_SET_GET_TEST(OSSL_CMP, CTX, N, M, DUP, FIELD, TYPE) \ argument 514 DEFINE_SET_GET_BASE_TEST(OSSL_CMP##_##CTX, set##N, get##M, DUP, FIELD, \ 529 #define DEFINE_SET_GET_TEST_DEFAULT(OSSL_CMP, CTX, N, M, DUP, FIELD, TYPE, \ argument 531 DEFINE_SET_GET_BASE_TEST(OSSL_CMP##_##CTX, set##N, get##M, DUP, FIELD, \ 533 #define DEFINE_SET_TEST_DEFAULT(OSSL_CMP, CTX, N, DUP, FIELD, TYPE, DEFAULT) \ argument 539 DEFINE_SET_GET_TEST_DEFAULT(OSSL_CMP, CTX, N, 0, DUP, FIELD, TYPE, DEFAULT) [all …]
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/freebsd/usr.bin/hexdump/ |
H A D | display.c | 269 if (vflag != DUP) { in get() 298 if (vflag == DUP || vflag == FIRST) in get() 306 vflag = DUP; in get()
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H A D | hexdump.h | 80 enum _vflag { ALL, DUP, FIRST, WAIT }; /* -v values */ enumerator
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMScheduleSwift.td | 933 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 935 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", 939 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$", 953 (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$", 954 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 957 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>; 960 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>; 964 (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$", 965 "VLD4(LN|DUP)( [all...] |
H A D | ARMScheduleA57.td | 145 "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm", 147 "VST(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm", 1276 "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 1278 "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", "VLD1LNq(8|16|32)Pseudo_UPD")>; 1293 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
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H A D | ARMScheduleM55.td | 350 def : InstRW<[M55Write2IntE2], (instregex "MVE_V(D|I)?W?DUP")>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 182 const TargetRegisterClass *FPRRegClass, unsigned DUP, in foldCopyDup() 207 if (!SrcMI || SrcMI->getOpcode() != DUP || !MRI.hasOneNonDBGUse(Src)) in foldCopyDup()
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/freebsd/stand/ficl/ |
H A D | vm.c | 180 DUP, 227 case DUP:
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/freebsd/crypto/heimdal/lib/kadm5/ |
H A D | kadm5_err.et | 18 error_code DUP, "Principal or policy already exists"
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/freebsd/crypto/openssl/util/ |
H A D | check-format-test-negatives.c | 421 #define DEFINE_SET_GET_BASE_TEST(PREFIX, SETN, GETN, DUP, FIELD, TYPE, ERR, \ argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedFalkorDetails.td | 909 def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>; 910 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>; 911 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(i8|i16|i32|i64)$")>; 937 def : InstRW<[FalkorWr_2GTOV_1cyc], (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>;
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H A D | AArch64SchedCyclone.td | 367 // DUP V,R 370 // DUP V,V[x] is a WriteV.
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H A D | AArch64SchedTSV110.td | 673 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>; 681 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
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H A D | AArch64ISelLowering.h | 186 DUP, enumerator
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H A D | AArch64SchedOryon.td | 1413 // ASIMD DUP element 1415 // ASIMD DUP general thoughput undecided, 3? FP0123
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H A D | AArch64SchedA55.td | 366 def : InstRW<[CortexA55WriteFPALU_F2], (instregex "^DUP(v2i64|v4i32|v8i16|v16i8)")>;
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H A D | AArch64ISelLowering.cpp | 2313 case AArch64ISD::DUP: { in computeKnownBitsForTargetNode() 2618 MAKE_CASE(AArch64ISD::DUP) in getTargetNodeName() 3243 if (N->getOpcode() != AArch64ISD::DUP) in isZerosVector() 5683 return DAG.getNode(AArch64ISD::DUP, dl, MVT::v1i64, N); in LowerINTRINSIC_WO_CHAIN() 13167 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(), in LowerVECTOR_SHUFFLE() 13173 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane)); in LowerVECTOR_SHUFFLE() 14143 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value); in LowerBUILD_VECTOR() 14207 Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue); in LowerBUILD_VECTOR() 14650 if (Op.getOpcode() != AArch64ISD::DUP && in isPow2Splat() 18863 if (N->getOpcode() == AArch64ISD::DUP || N->getOpcode() == ISD::SPLAT_VECTOR) in isConstantSplatVectorMaskForType() [all …]
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H A D | AArch64InstrInfo.td | 735 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>; 6594 // AdvSIMD scalar DUP instruction 6597 defm DUP : SIMDScalarDUP<"mov">; 6660 // AdvSIMD INS/DUP instructions 6679 // DUP from a 64-bit register to a 64-bit register is just a copy 6746 Instruction DUP, SDNodeXForm IdxXFORM> { 6749 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 6753 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 6764 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP, 6768 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; [all …]
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H A D | AArch64SchedExynosM3.td | 673 def : InstRW<[M3WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>;
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H A D | AArch64SchedKryoDetails.td | 573 (instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>; 579 (instregex "DUP(v16i8|v8i16|v4i32|v2i64)(gpr|lane)")>;
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H A D | AArch64SchedA57.td | 530 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUP(i8|i16|i32|i64)$")>;
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