| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
136 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
186 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); in MoveCopyOutOfITBlock()
202 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
225 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
243 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); in InsertITInstructions()
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| H A D | ARMLoadStoreOptimizer.cpp | 175 ARMCC::CondCodes Pred, unsigned PredReg);
179 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
489 ARMCC::CondCodes Pred, in UpdateBaseRegUses()
631 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
838 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
909 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); in MergeOpsUpdate()
1192 ARMCC::CondCodes Pred, Register PredReg) { in isIncrementOrDecrement()
1224 ARMCC::CondCodes Pred, Register PredReg, int &Offset) { in findIncDecBefore()
1244 ARMCC::CondCodes Pred, Register PredReg, int &Offset, in findIncDecAfter()
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| H A D | ARMBaseInstrInfo.h | 170 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
172 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() in getPredicate()
562 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
804 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
820 ARMCC::CondCodes Pred, Register PredReg,
827 ARMCC::CondCodes Pred, Register PredReg,
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| H A D | ThumbRegisterInfo.h | 42 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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| H A D | ARMInstructionSelector.cpp | 54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
393 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
395 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL}; in getComparePreds()
577 ARMCC::CondCodes Cond, in insertComparison()
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| H A D | Thumb2InstrInfo.h | 82 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
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| H A D | MLxExpansionPass.cpp | 281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
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| H A D | ThumbRegisterInfo.cpp | 65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| H A D | Thumb2SizeReduction.cpp | 187 bool is2Addr, ARMCC::CondCodes Pred,
331 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
893 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
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| H A D | ARMBaseRegisterInfo.cpp | 499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
850 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
851 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
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| H A D | ARMBaseRegisterInfo.h | 213 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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| H A D | ARMBaseInstrInfo.cpp | 218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); in convertToThreeAddress()
554 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in reverseBranchCondition()
598 CC += ARMCondCodeToString((ARMCC::CondCodes)Op.getImm()); in createMIROperandComment()
641 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
642 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
2233 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI, in getInstrPredicate()
2242 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in getInstrPredicate()
2265 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2378 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); in optimizeSelect()
2472 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate()
[all …]
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| H A D | Thumb2InstrInfo.cpp | 75 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
313 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
786 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI, in getITInstrPredicate()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode()
576 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
593 ARMCC::CondCodes ExpectedCode = GetCondCode(Cond); in IsVPNOTEquivalent()
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| H A D | ARMBlockPlacement.cpp | 280 MIB.addImm(ARMCC::CondCodes::AL); in moveBasicBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.h | 33 enum CondCodes { enum
71 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
72 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
73 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
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| H A D | AVRInstrInfo.cpp | 195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { in getBrCond()
218 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const { in getCondFromBranchOpc()
241 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const { in getOppositeCondition()
323 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); in analyzeBranch()
385 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
420 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
473 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Utils/ |
| H A D | ARMBaseInfo.h | 30 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
48 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
71 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { in getSwappedCondition()
146 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
219 MSP430CC::CondCodes BranchCode = in analyzeBranch()
220 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in analyzeBranch()
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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| H A D | MSP430.h | 22 enum CondCodes { enum
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | Sparc.h | 41 enum CondCodes { enum
105 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
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| H A D | SparcInstrInfo.cpp | 84 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
396 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm()); in reverseBranchCondition()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 28 enum CondCodes { enum
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 1007 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
1018 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS) in printMandatoryRestrictedPredicateOperand()
1028 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
1036 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryInvertedPredicateOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcInstPrinter.cpp | 214 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()
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