Searched refs:CVI_ZW (Results 1 – 14 of 14) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonScheduleV62.td | 23 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV69.td | 25 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV71.td | 24 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV73.td | 24 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV65.td | 25 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV66.td | 25 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV67.td | 25 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV68.td | 24 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonDepIICHVX.td | 265 InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2], 521 InstrStage<1, [CVI_ZW]>], [3, 1, 2], 651 InstrStage<1, [CVI_ZW]>], [2, 1, 2], 687 InstrStage<1, [CVI_ZW]>], [1, 2], 857 InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2], 1113 InstrStage<1, [CVI_ZW]>], [3, 1, 2], 1243 InstrStage<1, [CVI_ZW]>], [2, 1, 2], 1279 InstrStage<1, [CVI_ZW]>], [1, 2], 1449 InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2], 1705 InstrStage<1, [CVI_ZW]>], [3, 1, 2], [all …]
|
H A D | HexagonScheduleV67T.td | 47 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV71T.td | 46 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonScheduleV60.td | 67 CVI_ALL_NOMEM, CVI_ZW],
|
H A D | HexagonSchedule.td | 29 def CVI_ZW : FuncUnit; // Z register write port
|
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCTargetDesc.cpp | 182 CVI_ZW = 1 << 4 in HexagonConvertUnits() enumerator 206 else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW) in HexagonConvertUnits() 207 return (*Lanes = 1, CVI_ZW); in HexagonConvertUnits()
|