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Searched refs:CVI_ZW (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV62.td23 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV69.td25 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV71.td24 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV73.td24 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV65.td25 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV66.td25 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV67.td25 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV68.td24 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonDepIICHVX.td265 InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
521 InstrStage<1, [CVI_ZW]>], [3, 1, 2],
651 InstrStage<1, [CVI_ZW]>], [2, 1, 2],
687 InstrStage<1, [CVI_ZW]>], [1, 2],
857 InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
1113 InstrStage<1, [CVI_ZW]>], [3, 1, 2],
1243 InstrStage<1, [CVI_ZW]>], [2, 1, 2],
1279 InstrStage<1, [CVI_ZW]>], [1, 2],
1449 InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
1705 InstrStage<1, [CVI_ZW]>], [3, 1, 2],
[all …]
H A DHexagonScheduleV67T.td47 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV71T.td46 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonScheduleV60.td67 CVI_ALL_NOMEM, CVI_ZW],
H A DHexagonSchedule.td29 def CVI_ZW : FuncUnit; // Z register write port
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp182 CVI_ZW = 1 << 4 in HexagonConvertUnits() enumerator
206 else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW) in HexagonConvertUnits()
207 return (*Lanes = 1, CVI_ZW); in HexagonConvertUnits()