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Searched refs:CTLZ (Results 1 – 25 of 45) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3663 { ISD::CTLZ, MVT::v8i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3664 { ISD::CTLZ, MVT::v16i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3665 { ISD::CTLZ, MVT::v32i16, { 18, 27, 23, 27 } }, in getIntrinsicInstrCost()
3666 { ISD::CTLZ, MVT::v64i8, { 3, 16, 9, 11 } }, in getIntrinsicInstrCost()
3667 { ISD::CTLZ, MVT::v4i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3668 { ISD::CTLZ, MVT::v8i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3669 { ISD::CTLZ, MVT::v16i16, { 8, 19, 11, 13 } }, in getIntrinsicInstrCost()
3670 { ISD::CTLZ, MVT::v32i8, { 2, 11, 9, 10 } }, in getIntrinsicInstrCost()
3671 { ISD::CTLZ, MVT::v2i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3672 { ISD::CTLZ, MVT::v4i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp160 Function *CTLZ = in generateUnsignedDivisionCode() local
234 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp146 case ARC::CTLZ: in runOnMachineFunction()
H A DARCISelLowering.cpp172 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in ARCTargetLowering()
H A DARCInstrInfo.td137 def CTLZ : PseudoInstARC<(outs GPR32:$A),
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h767 CTLZ, enumerator
H A DSDPatternMatch.h1060 return UnaryOpc_match<Opnd>(ISD::CTLZ, Op);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandFp.cpp363 Function *CTLZ = in expandIToFP() local
378 Value *Call = Builder.CreateCall(CTLZ, {IsSigned ? Sub : IntVal, True}); in expandIToFP()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1964 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in SparcTargetLowering()
1965 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SparcTargetLowering()
1976 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in SparcTargetLowering()
1977 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in SparcTargetLowering()
1986 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in SparcTargetLowering()
1987 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in SparcTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp105 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
106 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp721 if (unsigned CTLZ = DemandedMask.countl_zero()) { in SimplifyDemandedUseBits() local
722 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedUseBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp485 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
510 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
514 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom); in AMDGPUTargetLowering()
532 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
1465 case ISD::CTLZ: in LowerOperation()
1503 case ISD::CTLZ: in ReplaceNodeResults()
3167 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
3346 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp206 setOperationAction(ISD::CTLZ, T, Legal); in initializeHVXLowering()
297 setOperationAction(ISD::CTLZ, T, Custom); in initializeHVXLowering()
1909 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)}); in LowerHvxCttz()
2908 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, InpTy, Abs); in ExpandHvxIntToFp()
3200 case ISD::CTLZ: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1646 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1647 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1720 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE, in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp510 case ISD::CTLZ: return "ctlz"; in getOperationName()
H A DTargetLowering.cpp1939 if (unsigned CTLZ = DemandedBits.countl_zero()) { in SimplifyDemandedBits() local
1940 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedBits()
4744 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
9390 isOperationLegalOrCustom(ISD::CTLZ, VT)) in expandCTLZ()
9391 return DAG.getNode(ISD::CTLZ, dl, VT, Op); in expandCTLZ()
9397 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); in expandCTLZ() local
9401 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ); in expandCTLZ()
9528 !isOperationLegalOrCustom(ISD::CTLZ, VT) && in expandCTTZ()
9538 !isOperationLegal(ISD::CTLZ, VT)) in expandCTTZ()
9551 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) { in expandCTTZ()
[all …]
H A DLegalizeVectorOps.cpp389 case ISD::CTLZ: in LegalizeOp()
1091 case ISD::CTLZ: in Expand()
H A DLegalizeIntegerTypes.cpp71 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
698 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) && in PromoteIntRes_CTLZ()
707 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) { in PromoteIntRes_CTLZ()
792 !TLI.isOperationLegal(ISD::CTLZ, NVT)) { in PromoteIntRes_CTTZ()
2975 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp641 ISD::BITREVERSE, ISD::CTLZ, ISD::CTPOP, ISD::CTTZ, in NVPTXTargetLowering()
791 setOperationAction({ISD::CTPOP, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i16, in NVPTXTargetLowering()
793 setOperationAction({ISD::CTPOP, ISD::CTLZ}, MVT::i32, Legal); in NVPTXTargetLowering()
794 setOperationAction({ISD::CTPOP, ISD::CTLZ}, MVT::i64, Custom); in NVPTXTargetLowering()
802 setI16x2OperationAction(ISD::CTLZ, MVT::v2i16, Legal, Expand); in NVPTXTargetLowering()
2969 case ISD::CTLZ: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp125 setOperationAction(ISD::CTLZ, VT, Expand); in BPFTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp277 setOperationAction(ISD::CTLZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
281 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering()
1683 case ISD::CTLZ: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def241 VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp120 setOperationAction(ISD::CTLZ, GRLenVT, Expand); in LoongArchTargetLowering()
149 setOperationAction(ISD::CTLZ, MVT::i32, Custom); in LoongArchTargetLowering()
304 setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal); in LoongArchTargetLowering()
371 setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal); in LoongArchTargetLowering()
3806 case ISD::CTLZ: in getLoongArchWOpcode()
4150 case ISD::CTLZ: in ReplaceNodeResults()
5566 return DAG.getNode(ISD::CTLZ, DL, N->getValueType(0), N->getOperand(1)); in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp98 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp125 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in LanaiTargetLowering()

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