| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3509 { ISD::CTLZ, MVT::v8i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3510 { ISD::CTLZ, MVT::v16i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3511 { ISD::CTLZ, MVT::v32i16, { 18, 27, 23, 27 } }, in getIntrinsicInstrCost()
3512 { ISD::CTLZ, MVT::v64i8, { 3, 16, 9, 11 } }, in getIntrinsicInstrCost()
3513 { ISD::CTLZ, MVT::v4i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3514 { ISD::CTLZ, MVT::v8i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3515 { ISD::CTLZ, MVT::v16i16, { 8, 19, 11, 13 } }, in getIntrinsicInstrCost()
3516 { ISD::CTLZ, MVT::v32i8, { 2, 11, 9, 10 } }, in getIntrinsicInstrCost()
3517 { ISD::CTLZ, MVT::v2i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3518 { ISD::CTLZ, MVT::v4i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 160 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
234 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCExpandPseudos.cpp | 146 case ARC::CTLZ: in runOnMachineFunction()
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| H A D | ARCISelLowering.cpp | 171 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in ARCTargetLowering()
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| H A D | ARCInstrInfo.td | 138 def CTLZ : PseudoInstARC<(outs GPR32:$A),
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 744 CTLZ, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandLargeFpConvert.cpp | 358 Function *CTLZ = in expandIToFP() local
373 Value *Call = Builder.CreateCall(CTLZ, {IsSigned ? Sub : IntVal, True}); in expandIToFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 106 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
107 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 706 if (unsigned CTLZ = DemandedMask.countl_zero()) { in SimplifyDemandedUseBits() local
707 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedUseBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 472 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
497 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
501 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom); in AMDGPUTargetLowering()
519 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
1408 case ISD::CTLZ: in LowerOperation()
1446 case ISD::CTLZ: in ReplaceNodeResults()
3109 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
3288 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 204 setOperationAction(ISD::CTLZ, T, Legal); in initializeHVXLowering()
293 setOperationAction(ISD::CTLZ, T, Custom); in initializeHVXLowering()
1869 // Lower vector CTTZ into a computation using CTLZ (Hacker's Delight): in LowerHvxCttz()
1894 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)}); in LowerHvxCttz()
2871 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, InpTy, Abs); in ExpandHvxIntToFp()
3163 case ISD::CTLZ: in LowerHvxOperation()
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| H A D | HexagonISelLowering.cpp | 1578 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1579 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1651 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 253 setOperationAction(ISD::CTLZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
257 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering()
1505 case ISD::CTLZ: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 488 case ISD::CTLZ: return "ctlz"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 378 case ISD::CTLZ: in LegalizeOp()
964 case ISD::CTLZ: in Expand()
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| H A D | TargetLowering.cpp | 1897 if (unsigned CTLZ = DemandedBits.countl_zero()) { in SimplifyDemandedBits() local
1898 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedBits()
4531 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
8985 isOperationLegalOrCustom(ISD::CTLZ, VT)) in expandCTLZ()
8986 return DAG.getNode(ISD::CTLZ, dl, VT, Op); in expandCTLZ()
8992 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); in expandCTLZ() local
8996 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ); in expandCTLZ()
9123 !isOperationLegalOrCustom(ISD::CTLZ, VT) && in expandCTTZ()
9132 !isOperationLegal(ISD::CTLZ, VT)) in expandCTTZ()
9145 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) { in expandCTTZ()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 71 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
658 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) && in PromoteIntRes_CTLZ()
667 if (CtlzOpcode == ISD::CTLZ || CtlzOpcode == ISD::VP_CTLZ) { in PromoteIntRes_CTLZ()
752 !TLI.isOperationLegal(ISD::CTLZ, NVT)) { in PromoteIntRes_CTTZ()
2792 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 117 setOperationAction(ISD::CTLZ, VT, Expand); in BPFTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 134 setOperationAction(ISD::CTLZ, MVT::i32, Custom); in LoongArchTargetLowering()
265 setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal); in LoongArchTargetLowering()
312 setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal); in LoongArchTargetLowering()
2637 case ISD::CTLZ: in getLoongArchWOpcode()
2929 case ISD::CTLZ: in ReplaceNodeResults()
4071 return DAG.getNode(ISD::CTLZ, DL, N->getValueType(0), N->getOperand(1)); in performINTRINSIC_WO_CHAINCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 269 VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 402 setOperationAction(ISD::CTLZ, MVT::i32, in RISCVTargetLowering()
407 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom); in RISCVTargetLowering()
410 setOperationAction(ISD::CTLZ, XLenVT, Expand); in RISCVTargetLowering()
412 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in RISCVTargetLowering()
915 setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand); in RISCVTargetLowering()
924 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, in RISCVTargetLowering()
1271 setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, in RISCVTargetLowering()
1280 {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in RISCVTargetLowering()
5510 // EltSize. Hence, we can do min(Res, EltSize) for CTLZ. in lowerCTLZ_CTTZ_ZERO_UNDEF()
5511 if (Op.getOpcode() == ISD::CTLZ) in lowerCTLZ_CTTZ_ZERO_UNDEF()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 98 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 127 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 278 setOperationAction(ISD::CTLZ, VT, Legal); in addMVEVectorTypes()
974 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in ARMTargetLowering()
975 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand); in ARMTargetLowering()
1209 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in ARMTargetLowering()
4143 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR); in LowerINTRINSIC_WO_CHAIN()
4160 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi); in LowerINTRINSIC_WO_CHAIN()
4167 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo); in LowerINTRINSIC_WO_CHAIN()
6546 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); in LowerCTTZ() local
6547 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ); in LowerCTTZ()
6571 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); in LowerCTTZ()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1754 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1816 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
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